cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ingenic-tcu.rst (2961B)

      1.. SPDX-License-Identifier: GPL-2.0
      2
      3===============================================
      4Ingenic JZ47xx SoCs Timer/Counter Unit hardware
      5===============================================
      6
      7The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
      8hardware block. It features up to eight channels, that can be used as
      9counters, timers, or PWM.
     10
     11- JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
     12  have eight channels.
     13
     14- JZ4725B introduced a separate channel, called Operating System Timer
     15  (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
     16  64-bit.
     17
     18- Each one of the TCU channels has its own clock, which can be reparented to three
     19  different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.
     20
     21    - The watchdog and OST hardware blocks also feature a TCSR register with the same
     22      format in their register space.
     23    - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
     24      OST clocks.
     25
     26- Each TCU channel works in one of two modes:
     27
     28    - mode TCU1: channels cannot work in sleep mode, but are easier to
     29      operate.
     30    - mode TCU2: channels can work in sleep mode, but the operation is a bit
     31      more complicated than with TCU1 channels.
     32
     33- The mode of each TCU channel depends on the SoC used:
     34
     35    - On the oldest SoCs (up to JZ4740), all of the eight channels operate in
     36      TCU1 mode.
     37    - On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.
     38    - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
     39      others operate as TCU1.
     40
     41- Each channel can generate an interrupt. Some channels share an interrupt
     42  line, some don't, and this changes between SoC versions:
     43
     44    - on older SoCs (JZ4740 and below), channel 0 and channel 1 have their
     45      own interrupt line; channels 2-7 share the last interrupt line.
     46    - On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one
     47      interrupt line; the OST uses the last interrupt line.
     48    - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt;
     49      channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
     50      the OST uses the last interrupt line.
     51
     52Implementation
     53==============
     54
     55The functionalities of the TCU hardware are spread across multiple drivers:
     56
     57===========  =====
     58clocks       drivers/clk/ingenic/tcu.c
     59interrupts   drivers/irqchip/irq-ingenic-tcu.c
     60timers       drivers/clocksource/ingenic-timer.c
     61OST          drivers/clocksource/ingenic-ost.c
     62PWM          drivers/pwm/pwm-jz4740.c
     63watchdog     drivers/watchdog/jz4740_wdt.c
     64===========  =====
     65
     66Because various functionalities of the TCU that belong to different drivers
     67and frameworks can be controlled from the same registers, all of these
     68drivers access their registers through the same regmap.
     69
     70For more information regarding the devicetree bindings of the TCU drivers,
     71have a look at Documentation/devicetree/bindings/timer/ingenic,tcu.yaml.