cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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eeprom.rst (4490B)


      1====================
      2Kernel driver eeprom
      3====================
      4
      5Supported chips:
      6
      7  * Any EEPROM chip in the designated address range
      8
      9    Prefix: 'eeprom'
     10
     11    Addresses scanned: I2C 0x50 - 0x57
     12
     13    Datasheets: Publicly available from:
     14
     15                Atmel (www.atmel.com),
     16                Catalyst (www.catsemi.com),
     17                Fairchild (www.fairchildsemi.com),
     18                Microchip (www.microchip.com),
     19                Philips (www.semiconductor.philips.com),
     20                Rohm (www.rohm.com),
     21                ST (www.st.com),
     22                Xicor (www.xicor.com),
     23                and others.
     24
     25        ========= ============= ============================================
     26        Chip      Size (bits)   Address
     27        ========= ============= ============================================
     28        24C01     1K            0x50 (shadows at 0x51 - 0x57)
     29        24C01A    1K            0x50 - 0x57 (Typical device on DIMMs)
     30        24C02     2K            0x50 - 0x57
     31        24C04     4K            0x50, 0x52, 0x54, 0x56
     32                                (additional data at 0x51, 0x53, 0x55, 0x57)
     33        24C08     8K            0x50, 0x54 (additional data at 0x51, 0x52,
     34                                0x53, 0x55, 0x56, 0x57)
     35        24C16     16K           0x50 (additional data at 0x51 - 0x57)
     36        Sony      2K            0x57
     37
     38        Atmel     34C02B  2K    0x50 - 0x57, SW write protect at 0x30-37
     39        Catalyst  34FC02  2K    0x50 - 0x57, SW write protect at 0x30-37
     40        Catalyst  34RC02  2K    0x50 - 0x57, SW write protect at 0x30-37
     41        Fairchild 34W02   2K    0x50 - 0x57, SW write protect at 0x30-37
     42        Microchip 24AA52  2K    0x50 - 0x57, SW write protect at 0x30-37
     43        ST        M34C02  2K    0x50 - 0x57, SW write protect at 0x30-37
     44        ========= ============= ============================================
     45
     46
     47Authors:
     48        - Frodo Looijaard <frodol@dds.nl>,
     49        - Philip Edelbrock <phil@netroedge.com>,
     50        - Jean Delvare <jdelvare@suse.de>,
     51        - Greg Kroah-Hartman <greg@kroah.com>,
     52        - IBM Corp.
     53
     54Description
     55-----------
     56
     57This is a simple EEPROM module meant to enable reading the first 256 bytes
     58of an EEPROM (on a SDRAM DIMM for example). However, it will access serial
     59EEPROMs on any I2C adapter. The supported devices are generically called
     6024Cxx, and are listed above; however the numbering for these
     61industry-standard devices may vary by manufacturer.
     62
     63This module was a programming exercise to get used to the new project
     64organization laid out by Frodo, but it should be at least completely
     65effective for decoding the contents of EEPROMs on DIMMs.
     66
     67DIMMS will typically contain a 24C01A or 24C02, or the 34C02 variants.
     68The other devices will not be found on a DIMM because they respond to more
     69than one address.
     70
     71DDC Monitors may contain any device. Often a 24C01, which responds to all 8
     72addresses, is found.
     73
     74Recent Sony Vaio laptops have an EEPROM at 0x57. We couldn't get the
     75specification, so it is guess work and far from being complete.
     76
     77The Microchip 24AA52/24LCS52, ST M34C02, and others support an additional
     78software write protect register at 0x30 - 0x37 (0x20 less than the memory
     79location). The chip responds to "write quick" detection at this address but
     80does not respond to byte reads. If this register is present, the lower 128
     81bytes of the memory array are not write protected. Any byte data write to
     82this address will write protect the memory array permanently, and the
     83device will no longer respond at the 0x30-37 address. The eeprom driver
     84does not support this register.
     85
     86Lacking functionality
     87---------------------
     88
     89* Full support for larger devices (24C04, 24C08, 24C16). These are not
     90  typically found on a PC. These devices will appear as separate devices at
     91  multiple addresses.
     92
     93* Support for really large devices (24C32, 24C64, 24C128, 24C256, 24C512).
     94  These devices require two-byte address fields and are not supported.
     95
     96* Enable Writing. Again, no technical reason why not, but making it easy
     97  to change the contents of the EEPROMs (on DIMMs anyway) also makes it easy
     98  to disable the DIMMs (potentially preventing the computer from booting)
     99  until the values are restored somehow.
    100
    101Use
    102---
    103
    104After inserting the module (and any other required SMBus/i2c modules), you
    105should have some EEPROM directories in ``/sys/bus/i2c/devices/*`` of names such
    106as "0-0050". Inside each of these is a series of files, the eeprom file
    107contains the binary data from EEPROM.