cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hinic.rst (4331B)


      1.. SPDX-License-Identifier: GPL-2.0
      2
      3============================================================
      4Linux Kernel Driver for Huawei Intelligent NIC(HiNIC) family
      5============================================================
      6
      7Overview:
      8=========
      9HiNIC is a network interface card for the Data Center Area.
     10
     11The driver supports a range of link-speed devices (10GbE, 25GbE, 40GbE, etc.).
     12The driver supports also a negotiated and extendable feature set.
     13
     14Some HiNIC devices support SR-IOV. This driver is used for Physical Function
     15(PF).
     16
     17HiNIC devices support MSI-X interrupt vector for each Tx/Rx queue and
     18adaptive interrupt moderation.
     19
     20HiNIC devices support also various offload features such as checksum offload,
     21TCP Transmit Segmentation Offload(TSO), Receive-Side Scaling(RSS) and
     22LRO(Large Receive Offload).
     23
     24
     25Supported PCI vendor ID/device IDs:
     26===================================
     27
     2819e5:1822 - HiNIC PF
     29
     30
     31Driver Architecture and Source Code:
     32====================================
     33
     34hinic_dev - Implement a Logical Network device that is independent from
     35specific HW details about HW data structure formats.
     36
     37hinic_hwdev - Implement the HW details of the device and include the components
     38for accessing the PCI NIC.
     39
     40hinic_hwdev contains the following components:
     41===============================================
     42
     43HW Interface:
     44=============
     45
     46The interface for accessing the pci device (DMA memory and PCI BARs).
     47(hinic_hw_if.c, hinic_hw_if.h)
     48
     49Configuration Status Registers Area that describes the HW Registers on the
     50configuration and status BAR0. (hinic_hw_csr.h)
     51
     52MGMT components:
     53================
     54
     55Asynchronous Event Queues(AEQs) - The event queues for receiving messages from
     56the MGMT modules on the cards. (hinic_hw_eqs.c, hinic_hw_eqs.h)
     57
     58Application Programmable Interface commands(API CMD) - Interface for sending
     59MGMT commands to the card. (hinic_hw_api_cmd.c, hinic_hw_api_cmd.h)
     60
     61Management (MGMT) - the PF to MGMT channel that uses API CMD for sending MGMT
     62commands to the card and receives notifications from the MGMT modules on the
     63card by AEQs. Also set the addresses of the IO CMDQs in HW.
     64(hinic_hw_mgmt.c, hinic_hw_mgmt.h)
     65
     66IO components:
     67==============
     68
     69Completion Event Queues(CEQs) - The completion Event Queues that describe IO
     70tasks that are finished. (hinic_hw_eqs.c, hinic_hw_eqs.h)
     71
     72Work Queues(WQ) - Contain the memory and operations for use by CMD queues and
     73the Queue Pairs. The WQ is a Memory Block in a Page. The Block contains
     74pointers to Memory Areas that are the Memory for the Work Queue Elements(WQEs).
     75(hinic_hw_wq.c, hinic_hw_wq.h)
     76
     77Command Queues(CMDQ) - The queues for sending commands for IO management and is
     78used to set the QPs addresses in HW. The commands completion events are
     79accumulated on the CEQ that is configured to receive the CMDQ completion events.
     80(hinic_hw_cmdq.c, hinic_hw_cmdq.h)
     81
     82Queue Pairs(QPs) - The HW Receive and Send queues for Receiving and Transmitting
     83Data. (hinic_hw_qp.c, hinic_hw_qp.h, hinic_hw_qp_ctxt.h)
     84
     85IO - de/constructs all the IO components. (hinic_hw_io.c, hinic_hw_io.h)
     86
     87HW device:
     88==========
     89
     90HW device - de/constructs the HW Interface, the MGMT components on the
     91initialization of the driver and the IO components on the case of Interface
     92UP/DOWN Events. (hinic_hw_dev.c, hinic_hw_dev.h)
     93
     94
     95hinic_dev contains the following components:
     96===============================================
     97
     98PCI ID table - Contains the supported PCI Vendor/Device IDs.
     99(hinic_pci_tbl.h)
    100
    101Port Commands - Send commands to the HW device for port management
    102(MAC, Vlan, MTU, ...). (hinic_port.c, hinic_port.h)
    103
    104Tx Queues - Logical Tx Queues that use the HW Send Queues for transmit.
    105The Logical Tx queue is not dependent on the format of the HW Send Queue.
    106(hinic_tx.c, hinic_tx.h)
    107
    108Rx Queues - Logical Rx Queues that use the HW Receive Queues for receive.
    109The Logical Rx queue is not dependent on the format of the HW Receive Queue.
    110(hinic_rx.c, hinic_rx.h)
    111
    112hinic_dev - de/constructs the Logical Tx and Rx Queues.
    113(hinic_main.c, hinic_dev.h)
    114
    115
    116Miscellaneous
    117=============
    118
    119Common functions that are used by HW and Logical Device.
    120(hinic_common.c, hinic_common.h)
    121
    122
    123Support
    124=======
    125
    126If an issue is identified with the released source code on the supported kernel
    127with a supported adapter, email the specific information related to the issue to
    128aviad.krawczyk@huawei.com.