qlge.rst (4276B)
1.. SPDX-License-Identifier: GPL-2.0 2 3======================================= 4QLogic QLGE 10Gb Ethernet device driver 5======================================= 6 7This driver use drgn and devlink for debugging. 8 9Dump kernel data structures in drgn 10----------------------------------- 11 12To dump kernel data structures, the following Python script can be used 13in drgn: 14 15.. code-block:: python 16 17 def align(x, a): 18 """the alignment a should be a power of 2 19 """ 20 mask = a - 1 21 return (x+ mask) & ~mask 22 23 def struct_size(struct_type): 24 struct_str = "struct {}".format(struct_type) 25 return sizeof(Object(prog, struct_str, address=0x0)) 26 27 def netdev_priv(netdevice): 28 NETDEV_ALIGN = 32 29 return netdevice.value_() + align(struct_size("net_device"), NETDEV_ALIGN) 30 31 name = 'xxx' 32 qlge_device = None 33 netdevices = prog['init_net'].dev_base_head.address_of_() 34 for netdevice in list_for_each_entry("struct net_device", netdevices, "dev_list"): 35 if netdevice.name.string_().decode('ascii') == name: 36 print(netdevice.name) 37 38 ql_adapter = Object(prog, "struct ql_adapter", address=netdev_priv(qlge_device)) 39 40The struct ql_adapter will be printed in drgn as follows, 41 42 >>> ql_adapter 43 (struct ql_adapter){ 44 .ricb = (struct ricb){ 45 .base_cq = (u8)0, 46 .flags = (u8)120, 47 .mask = (__le16)26637, 48 .hash_cq_id = (u8 [1024]){ 172, 142, 255, 255 }, 49 .ipv6_hash_key = (__le32 [10]){}, 50 .ipv4_hash_key = (__le32 [4]){}, 51 }, 52 .flags = (unsigned long)0, 53 .wol = (u32)0, 54 .nic_stats = (struct nic_stats){ 55 .tx_pkts = (u64)0, 56 .tx_bytes = (u64)0, 57 .tx_mcast_pkts = (u64)0, 58 .tx_bcast_pkts = (u64)0, 59 .tx_ucast_pkts = (u64)0, 60 .tx_ctl_pkts = (u64)0, 61 .tx_pause_pkts = (u64)0, 62 ... 63 }, 64 .active_vlans = (unsigned long [64]){ 65 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 52780853100545, 18446744073709551615, 66 18446619461681283072, 0, 42949673024, 2147483647, 67 }, 68 .rx_ring = (struct rx_ring [17]){ 69 { 70 .cqicb = (struct cqicb){ 71 .msix_vect = (u8)0, 72 .reserved1 = (u8)0, 73 .reserved2 = (u8)0, 74 .flags = (u8)0, 75 .len = (__le16)0, 76 .rid = (__le16)0, 77 ... 78 }, 79 .cq_base = (void *)0x0, 80 .cq_base_dma = (dma_addr_t)0, 81 } 82 ... 83 } 84 } 85 86coredump via devlink 87-------------------- 88 89 90And the coredump obtained via devlink in json format looks like, 91 92.. code:: shell 93 94 $ devlink health dump show DEVICE reporter coredump -p -j 95 { 96 "Core Registers": { 97 "segment": 1, 98 "values": [ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ] 99 }, 100 "Test Logic Regs": { 101 "segment": 2, 102 "values": [ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ] 103 }, 104 "RMII Registers": { 105 "segment": 3, 106 "values": [ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ] 107 }, 108 ... 109 "Sem Registers": { 110 "segment": 50, 111 "values": [ 0,0,0,0 ] 112 } 113 } 114 115When the module parameter qlge_force_coredump is set to be true, the MPI 116RISC reset before coredumping. So coredumping will much longer since 117devlink tool has to wait for 5 secs for the resetting to be 118finished.