cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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openrisc_port.rst (4045B)


      1==============
      2OpenRISC Linux
      3==============
      4
      5This is a port of Linux to the OpenRISC class of microprocessors; the initial
      6target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
      7
      8For information about OpenRISC processors and ongoing development:
      9
     10	=======		=============================
     11	website		https://openrisc.io
     12	email		openrisc@lists.librecores.org
     13	=======		=============================
     14
     15---------------------------------------------------------------------
     16
     17Build instructions for OpenRISC toolchain and Linux
     18===================================================
     19
     20In order to build and run Linux for OpenRISC, you'll need at least a basic
     21toolchain and, perhaps, the architectural simulator.  Steps to get these bits
     22in place are outlined here.
     23
     241) Toolchain
     25
     26Toolchain binaries can be obtained from openrisc.io or our github releases page.
     27Instructions for building the different toolchains can be found on openrisc.io
     28or Stafford's toolchain build and release scripts.
     29
     30	==========	=================================================
     31	binaries	https://github.com/openrisc/or1k-gcc/releases
     32	toolchains	https://openrisc.io/software
     33	building	https://github.com/stffrdhrn/or1k-toolchain-build
     34	==========	=================================================
     35
     362) Building
     37
     38Build the Linux kernel as usual::
     39
     40	make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig
     41	make ARCH=openrisc CROSS_COMPILE="or1k-linux-"
     42
     433) Running on FPGA (optional)
     44
     45The OpenRISC community typically uses FuseSoC to manage building and programming
     46an SoC into an FPGA.  The below is an example of programming a De0 Nano
     47development board with the OpenRISC SoC.  During the build FPGA RTL is code
     48downloaded from the FuseSoC IP cores repository and built using the FPGA vendor
     49tools.  Binaries are loaded onto the board with openocd.
     50
     51::
     52
     53	git clone https://github.com/olofk/fusesoc
     54	cd fusesoc
     55	sudo pip install -e .
     56
     57	fusesoc init
     58	fusesoc build de0_nano
     59	fusesoc pgm de0_nano
     60
     61	openocd -f interface/altera-usb-blaster.cfg \
     62		-f board/or1k_generic.cfg
     63
     64	telnet localhost 4444
     65	> init
     66	> halt; load_image vmlinux ; reset
     67
     684) Running on a Simulator (optional)
     69
     70QEMU is a processor emulator which we recommend for simulating the OpenRISC
     71platform.  Please follow the OpenRISC instructions on the QEMU website to get
     72Linux running on QEMU.  You can build QEMU yourself, but your Linux distribution
     73likely provides binary packages to support OpenRISC.
     74
     75	=============	======================================================
     76	qemu openrisc	https://wiki.qemu.org/Documentation/Platforms/OpenRISC
     77	=============	======================================================
     78
     79---------------------------------------------------------------------
     80
     81Terminology
     82===========
     83
     84In the code, the following particles are used on symbols to limit the scope
     85to more or less specific processor implementations:
     86
     87========= =======================================
     88openrisc: the OpenRISC class of processors
     89or1k:     the OpenRISC 1000 family of processors
     90or1200:   the OpenRISC 1200 processor
     91========= =======================================
     92
     93---------------------------------------------------------------------
     94
     95History
     96========
     97
     9818-11-2003	Matjaz Breskvar (phoenix@bsemi.com)
     99	initial port of linux to OpenRISC/or32 architecture.
    100        all the core stuff is implemented and seams usable.
    101
    10208-12-2003	Matjaz Breskvar (phoenix@bsemi.com)
    103	complete change of TLB miss handling.
    104	rewrite of exceptions handling.
    105	fully functional sash-3.6 in default initrd.
    106	a much improved version with changes all around.
    107
    10810-04-2004	Matjaz Breskvar (phoenix@bsemi.com)
    109	alot of bugfixes all over.
    110	ethernet support, functional http and telnet servers.
    111	running many standard linux apps.
    112
    11326-06-2004	Matjaz Breskvar (phoenix@bsemi.com)
    114	port to 2.6.x
    115
    11630-11-2004	Matjaz Breskvar (phoenix@bsemi.com)
    117	lots of bugfixes and enhancments.
    118	added opencores framebuffer driver.
    119
    12009-10-2010    Jonas Bonn (jonas@southpole.se)
    121	major rewrite to bring up to par with upstream Linux 2.6.36