cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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isa-versions.rst (2164B)

      1==========================
      2CPU to ISA Version Mapping
      3==========================
      4
      5Mapping of some CPU versions to relevant ISA versions.
      6
      7========= ====================================================================
      8CPU       Architecture version
      9========= ====================================================================
     10Power10   Power ISA v3.1
     11Power9    Power ISA v3.0B
     12Power8    Power ISA v2.07
     13Power7    Power ISA v2.06
     14Power6    Power ISA v2.05
     15PA6T      Power ISA v2.04
     16Cell PPU  - Power ISA v2.02 with some minor exceptions
     17          - Plus Altivec/VMX ~= 2.03
     18Power5++  Power ISA v2.04 (no VMX)
     19Power5+   Power ISA v2.03
     20Power5    - PowerPC User Instruction Set Architecture Book I v2.02
     21          - PowerPC Virtual Environment Architecture Book II v2.02
     22          - PowerPC Operating Environment Architecture Book III v2.02
     23PPC970    - PowerPC User Instruction Set Architecture Book I v2.01
     24          - PowerPC Virtual Environment Architecture Book II v2.01
     25          - PowerPC Operating Environment Architecture Book III v2.01
     26          - Plus Altivec/VMX ~= 2.03
     27========= ====================================================================
     28
     29
     30Key Features
     31------------
     32
     33========== ==================
     34CPU        VMX (aka. Altivec)
     35========== ==================
     36Power10    Yes
     37Power9     Yes
     38Power8     Yes
     39Power7     Yes
     40Power6     Yes
     41PA6T       Yes
     42Cell PPU   Yes
     43Power5++   No
     44Power5+    No
     45Power5     No
     46PPC970     Yes
     47========== ==================
     48
     49========== ====
     50CPU        VSX
     51========== ====
     52Power10    Yes
     53Power9     Yes
     54Power8     Yes
     55Power7     Yes
     56Power6     No
     57PA6T       No
     58Cell PPU   No
     59Power5++   No
     60Power5+    No
     61Power5     No
     62PPC970     No
     63========== ====
     64
     65========== ====================================
     66CPU        Transactional Memory
     67========== ====================================
     68Power10    No  (* see Power ISA v3.1, "Appendix A. Notes on the Removal of Transactional Memory from the Architecture")
     69Power9     Yes (* see transactional_memory.txt)
     70Power8     Yes
     71Power7     No
     72Power6     No
     73PA6T       No
     74Cell PPU   No
     75Power5++   No
     76Power5+    No
     77Power5     No
     78PPC970     No
     79========== ====================================