cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

dai.rst (2316B)


      1==================================
      2ASoC Digital Audio Interface (DAI)
      3==================================
      4
      5ASoC currently supports the three main Digital Audio Interfaces (DAI) found on
      6SoC controllers and portable audio CODECs today, namely AC97, I2S and PCM.
      7
      8
      9AC97
     10====
     11
     12AC97 is a five wire interface commonly found on many PC sound cards. It is
     13now also popular in many portable devices. This DAI has a reset line and time
     14multiplexes its data on its SDATA_OUT (playback) and SDATA_IN (capture) lines.
     15The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
     16frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97
     17frame is 21uS long and is divided into 13 time slots.
     18
     19The AC97 specification can be found at :
     20https://www.intel.com/p/en_US/business/design
     21
     22
     23I2S
     24===
     25
     26I2S is a common 4 wire DAI used in HiFi, STB and portable devices. The Tx and
     27Rx lines are used for audio transmission, while the bit clock (BCLK) and
     28left/right clock (LRC) synchronise the link. I2S is flexible in that either the
     29controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
     30usually varies depending on the sample rate and the master system clock
     31(SYSCLK). LRCLK is the same as the sample rate. A few devices support separate
     32ADC and DAC LRCLKs, this allows for simultaneous capture and playback at
     33different sample rates.
     34
     35I2S has several different operating modes:-
     36
     37I2S
     38  MSB is transmitted on the falling edge of the first BCLK after LRC
     39  transition.
     40
     41Left Justified
     42  MSB is transmitted on transition of LRC.
     43
     44Right Justified
     45  MSB is transmitted sample size BCLKs before LRC transition.
     46
     47PCM
     48===
     49
     50PCM is another 4 wire interface, very similar to I2S, which can support a more
     51flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
     52to synchronise the link while the Tx and Rx lines are used to transmit and
     53receive the audio data. Bit clock usually varies depending on sample rate
     54while sync runs at the sample rate. PCM also supports Time Division
     55Multiplexing (TDM) in that several devices can use the bus simultaneously (this
     56is sometimes referred to as network mode).
     57
     58Common PCM operating modes:-
     59
     60Mode A
     61  MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
     62
     63Mode B
     64  MSB is transmitted on rising edge of FRAME/SYNC.