cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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events-msr.rst (783B)


      1================
      2MSR Trace Events
      3================
      4
      5The x86 kernel supports tracing most MSR (Model Specific Register) accesses.
      6To see the definition of the MSRs on Intel systems please see the SDM
      7at https://www.intel.com/sdm (Volume 3)
      8
      9Available trace points:
     10
     11/sys/kernel/debug/tracing/events/msr/
     12
     13Trace MSR reads:
     14
     15read_msr
     16
     17  - msr: MSR number
     18  - val: Value written
     19  - failed: 1 if the access failed, otherwise 0
     20
     21
     22Trace MSR writes:
     23
     24write_msr
     25
     26  - msr: MSR number
     27  - val: Value written
     28  - failed: 1 if the access failed, otherwise 0
     29
     30
     31Trace RDPMC in kernel:
     32
     33rdpmc
     34
     35The trace data can be post processed with the postprocess/decode_msr.py script::
     36
     37  cat /sys/kernel/debug/tracing/trace | decode_msr.py /usr/src/linux/include/asm/msr-index.h
     38
     39to add symbolic MSR names.
     40