cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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IO-APIC.rst (4925B)


      1.. SPDX-License-Identifier: GPL-2.0
      2
      3=======
      4IO-APIC
      5=======
      6
      7:Author: Ingo Molnar <mingo@kernel.org>
      8
      9Most (all) Intel-MP compliant SMP boards have the so-called 'IO-APIC',
     10which is an enhanced interrupt controller. It enables us to route
     11hardware interrupts to multiple CPUs, or to CPU groups. Without an
     12IO-APIC, interrupts from hardware will be delivered only to the
     13CPU which boots the operating system (usually CPU#0).
     14
     15Linux supports all variants of compliant SMP boards, including ones with
     16multiple IO-APICs. Multiple IO-APICs are used in high-end servers to
     17distribute IRQ load further.
     18
     19There are (a few) known breakages in certain older boards, such bugs are
     20usually worked around by the kernel. If your MP-compliant SMP board does
     21not boot Linux, then consult the linux-smp mailing list archives first.
     22
     23If your box boots fine with enabled IO-APIC IRQs, then your
     24/proc/interrupts will look like this one::
     25
     26  hell:~> cat /proc/interrupts
     27             CPU0
     28    0:    1360293    IO-APIC-edge  timer
     29    1:          4    IO-APIC-edge  keyboard
     30    2:          0          XT-PIC  cascade
     31   13:          1          XT-PIC  fpu
     32   14:       1448    IO-APIC-edge  ide0
     33   16:      28232   IO-APIC-level  Intel EtherExpress Pro 10/100 Ethernet
     34   17:      51304   IO-APIC-level  eth0
     35  NMI:          0
     36  ERR:          0
     37  hell:~>
     38
     39Some interrupts are still listed as 'XT PIC', but this is not a problem;
     40none of those IRQ sources is performance-critical.
     41
     42
     43In the unlikely case that your board does not create a working mp-table,
     44you can use the pirq= boot parameter to 'hand-construct' IRQ entries. This
     45is non-trivial though and cannot be automated. One sample /etc/lilo.conf
     46entry::
     47
     48	append="pirq=15,11,10"
     49
     50The actual numbers depend on your system, on your PCI cards and on their
     51PCI slot position. Usually PCI slots are 'daisy chained' before they are
     52connected to the PCI chipset IRQ routing facility (the incoming PIRQ1-4
     53lines)::
     54
     55               ,-.        ,-.        ,-.        ,-.        ,-.
     56     PIRQ4 ----| |-.    ,-| |-.    ,-| |-.    ,-| |--------| |
     57               |S|  \  /  |S|  \  /  |S|  \  /  |S|        |S|
     58     PIRQ3 ----|l|-. `/---|l|-. `/---|l|-. `/---|l|--------|l|
     59               |o|  \/    |o|  \/    |o|  \/    |o|        |o|
     60     PIRQ2 ----|t|-./`----|t|-./`----|t|-./`----|t|--------|t|
     61               |1| /\     |2| /\     |3| /\     |4|        |5|
     62     PIRQ1 ----| |-  `----| |-  `----| |-  `----| |--------| |
     63               `-'        `-'        `-'        `-'        `-'
     64
     65Every PCI card emits a PCI IRQ, which can be INTA, INTB, INTC or INTD::
     66
     67                               ,-.
     68                         INTD--| |
     69                               |S|
     70                         INTC--|l|
     71                               |o|
     72                         INTB--|t|
     73                               |x|
     74                         INTA--| |
     75                               `-'
     76
     77These INTA-D PCI IRQs are always 'local to the card', their real meaning
     78depends on which slot they are in. If you look at the daisy chaining diagram,
     79a card in slot4, issuing INTA IRQ, it will end up as a signal on PIRQ4 of
     80the PCI chipset. Most cards issue INTA, this creates optimal distribution
     81between the PIRQ lines. (distributing IRQ sources properly is not a
     82necessity, PCI IRQs can be shared at will, but it's a good for performance
     83to have non shared interrupts). Slot5 should be used for videocards, they
     84do not use interrupts normally, thus they are not daisy chained either.
     85
     86so if you have your SCSI card (IRQ11) in Slot1, Tulip card (IRQ9) in
     87Slot2, then you'll have to specify this pirq= line::
     88
     89	append="pirq=11,9"
     90
     91the following script tries to figure out such a default pirq= line from
     92your PCI configuration::
     93
     94	echo -n pirq=; echo `scanpci | grep T_L | cut -c56-` | sed 's/ /,/g'
     95
     96note that this script won't work if you have skipped a few slots or if your
     97board does not do default daisy-chaining. (or the IO-APIC has the PIRQ pins
     98connected in some strange way). E.g. if in the above case you have your SCSI
     99card (IRQ11) in Slot3, and have Slot1 empty::
    100
    101	append="pirq=0,9,11"
    102
    103[value '0' is a generic 'placeholder', reserved for empty (or non-IRQ emitting)
    104slots.]
    105
    106Generally, it's always possible to find out the correct pirq= settings, just
    107permute all IRQ numbers properly ... it will take some time though. An
    108'incorrect' pirq line will cause the booting process to hang, or a device
    109won't function properly (e.g. if it's inserted as a module).
    110
    111If you have 2 PCI buses, then you can use up to 8 pirq values, although such
    112boards tend to have a good configuration.
    113
    114Be prepared that it might happen that you need some strange pirq line::
    115
    116	append="pirq=0,0,0,0,0,0,9,11"
    117
    118Use smart trial-and-error techniques to find out the correct pirq line ...
    119
    120Good luck and mail to linux-smp@vger.kernel.org or
    121linux-kernel@vger.kernel.org if you have any problems that are not covered
    122by this document.
    123