cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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serial.h (1034B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * include/asm-alpha/serial.h
      4 */
      5
      6
      7/*
      8 * This assumes you have a 1.8432 MHz clock for your UART.
      9 *
     10 * It'd be nice if someone built a serial card with a 24.576 MHz
     11 * clock, since the 16550A is capable of handling a top speed of 1.5
     12 * megabits/second; but this requires the faster clock.
     13 */
     14#define BASE_BAUD ( 1843200 / 16 )
     15
     16/* Standard COM flags (except for COM4, because of the 8514 problem) */
     17#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
     18#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ)
     19#define STD_COM4_FLAGS (UPF_BOOT_AUTOCONF | UPF_AUTO_IRQ)
     20#else
     21#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
     22#define STD_COM4_FLAGS UPF_BOOT_AUTOCONF
     23#endif
     24
     25#define SERIAL_PORT_DFNS			\
     26	/* UART CLK   PORT IRQ     FLAGS        */			\
     27	{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },	/* ttyS0 */	\
     28	{ 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },	/* ttyS1 */	\
     29	{ 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },	/* ttyS2 */	\
     30	{ 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },	/* ttyS3 */