cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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wrperfmon.h (2623B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Definitions for use with the Alpha wrperfmon PAL call.
      4 */
      5
      6#ifndef __ALPHA_WRPERFMON_H
      7#define __ALPHA_WRPERFMON_H
      8
      9/* Following commands are implemented on all CPUs */
     10#define PERFMON_CMD_DISABLE 0
     11#define PERFMON_CMD_ENABLE 1
     12#define PERFMON_CMD_DESIRED_EVENTS 2
     13#define PERFMON_CMD_LOGGING_OPTIONS 3
     14/* Following commands on EV5/EV56/PCA56 only */
     15#define PERFMON_CMD_INT_FREQ 4
     16#define PERFMON_CMD_ENABLE_CLEAR 7
     17/* Following commands are on EV5 and better CPUs */
     18#define PERFMON_CMD_READ 5
     19#define PERFMON_CMD_WRITE 6
     20/* Following command are on EV6 and better CPUs */
     21#define PERFMON_CMD_ENABLE_WRITE 7
     22/* Following command are on EV67 and better CPUs */
     23#define PERFMON_CMD_I_STAT 8
     24#define PERFMON_CMD_PMPC 9
     25
     26
     27/* EV5/EV56/PCA56 Counters */
     28#define EV5_PCTR_0 (1UL<<0)
     29#define EV5_PCTR_1 (1UL<<1)
     30#define EV5_PCTR_2 (1UL<<2)
     31
     32#define EV5_PCTR_0_COUNT_SHIFT 48
     33#define EV5_PCTR_1_COUNT_SHIFT 32
     34#define EV5_PCTR_2_COUNT_SHIFT 16
     35
     36#define EV5_PCTR_0_COUNT_MASK 0xffffUL
     37#define EV5_PCTR_1_COUNT_MASK 0xffffUL
     38#define EV5_PCTR_2_COUNT_MASK 0x3fffUL
     39
     40/* EV6 Counters */
     41#define EV6_PCTR_0 (1UL<<0)
     42#define EV6_PCTR_1 (1UL<<1)
     43
     44#define EV6_PCTR_0_COUNT_SHIFT 28
     45#define EV6_PCTR_1_COUNT_SHIFT 6
     46
     47#define EV6_PCTR_0_COUNT_MASK 0xfffffUL
     48#define EV6_PCTR_1_COUNT_MASK 0xfffffUL
     49
     50/* EV67 (and subsequent) counters */
     51#define EV67_PCTR_0 (1UL<<0)
     52#define EV67_PCTR_1 (1UL<<1)
     53
     54#define EV67_PCTR_0_COUNT_SHIFT 28
     55#define EV67_PCTR_1_COUNT_SHIFT 6
     56
     57#define EV67_PCTR_0_COUNT_MASK 0xfffffUL
     58#define EV67_PCTR_1_COUNT_MASK 0xfffffUL
     59
     60
     61/*
     62 * The Alpha Architecure Handbook, vers. 4 (1998) appears to have a misprint
     63 *  in Table E-23 regarding the bits that set the event PCTR 1 counts.
     64 *  Hopefully what we have here is correct.
     65 */
     66#define EV6_PCTR_0_EVENT_MASK 0x10UL
     67#define EV6_PCTR_1_EVENT_MASK 0x0fUL
     68
     69/* EV6 Events */
     70#define EV6_PCTR_0_CYCLES (0UL << 4)
     71#define EV6_PCTR_0_INSTRUCTIONS (1UL << 4)
     72
     73#define EV6_PCTR_1_CYCLES 0
     74#define EV6_PCTR_1_BRANCHES 1
     75#define EV6_PCTR_1_BRANCH_MISPREDICTS 2
     76#define EV6_PCTR_1_DTB_SINGLE_MISSES 3
     77#define EV6_PCTR_1_DTB_DOUBLE_MISSES 4
     78#define EV6_PCTR_1_ITB_MISSES 5
     79#define EV6_PCTR_1_UNALIGNED_TRAPS 6
     80#define EV6_PCTR_1_REPLY_TRAPS 7
     81
     82/* From the Alpha Architecture Reference Manual, 4th edn., 2002 */
     83#define EV67_PCTR_MODE_MASK 0x10UL
     84#define EV67_PCTR_EVENT_MASK 0x0CUL
     85
     86#define EV67_PCTR_MODE_PROFILEME (1UL<<4)
     87#define EV67_PCTR_MODE_AGGREGATE (0UL<<4)
     88
     89#define EV67_PCTR_INSTR_CYCLES (0UL<<2)
     90#define EV67_PCTR_CYCLES_UNDEF (1UL<<2)
     91#define EV67_PCTR_INSTR_BCACHEMISS (2UL<<2)
     92#define EV67_PCTR_CYCLES_MBOX (3UL<<2)
     93
     94#endif