cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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vdk_axs10x_mb.dtsi (2884B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Support for peripherals on the AXS10x mainboard (VDK version)
      4 *
      5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
      6 */
      7
      8/ {
      9	axs10x_mb_vdk {
     10		compatible = "simple-bus";
     11		#address-cells = <1>;
     12		#size-cells = <1>;
     13		ranges = <0x00000000 0xe0000000 0x10000000>;
     14		interrupt-parent = <&mb_intc>;
     15
     16		clocks {
     17			apbclk: apbclk {
     18				compatible = "fixed-clock";
     19				clock-frequency = <50000000>;
     20				#clock-cells = <0>;
     21			};
     22
     23			mmcclk: mmcclk {
     24				compatible = "fixed-clock";
     25				clock-frequency = <50000000>;
     26				#clock-cells = <0>;
     27			};
     28
     29			pguclk: pguclk {
     30				#clock-cells = <0>;
     31				compatible = "fixed-clock";
     32				clock-frequency = <25175000>;
     33			};
     34		};
     35
     36		ethernet@18000 {
     37			#interrupt-cells = <1>;
     38			compatible = "snps,dwmac";
     39			reg = < 0x18000 0x2000 >;
     40			interrupts = < 4 >;
     41			interrupt-names = "macirq";
     42			phy-mode = "rgmii";
     43			snps,phy-addr = < 0 >;  // VDK model phy address is 0
     44			snps,pbl = < 32 >;
     45			clocks = <&apbclk>;
     46			clock-names = "stmmaceth";
     47		};
     48
     49		ehci@40000 {
     50			compatible = "generic-ehci";
     51			reg = < 0x40000 0x100 >;
     52			interrupts = < 8 >;
     53		};
     54
     55		uart@20000 {
     56			compatible = "snps,dw-apb-uart";
     57			reg = <0x20000 0x100>;
     58			clock-frequency = <2403200>;
     59			interrupts = <17>;
     60			baud = <115200>;
     61			reg-shift = <2>;
     62			reg-io-width = <4>;
     63		};
     64
     65		uart@21000 {
     66			compatible = "snps,dw-apb-uart";
     67			reg = <0x21000 0x100>;
     68			clock-frequency = <2403200>;
     69			interrupts = <18>;
     70			baud = <115200>;
     71			reg-shift = <2>;
     72			reg-io-width = <4>;
     73		};
     74
     75		uart@22000 {
     76			compatible = "snps,dw-apb-uart";
     77			reg = <0x22000 0x100>;
     78			clock-frequency = <2403200>;
     79			interrupts = <19>;
     80			baud = <115200>;
     81			reg-shift = <2>;
     82			reg-io-width = <4>;
     83		};
     84
     85/* PGU output directly sent to virtual LCD screen; hdmi controller not modelled */
     86		pgu@17000 {
     87			compatible = "snps,arcpgu";
     88			reg = <0x17000 0x400>;
     89			clocks = <&pguclk>;
     90			clock-names = "pxlclk";
     91		};
     92
     93/* VDK has additional ps2 keyboard/mouse interface integrated in LCD screen model */
     94		ps2: ps2@e0017400 {
     95			compatible = "snps,arc_ps2";
     96			reg = <0x17400 0x14>;
     97			interrupts = <5>;
     98			interrupt-names = "arc_ps2_irq";
     99		};
    100
    101		mmc@15000 {
    102			compatible = "snps,dw-mshc";
    103			reg = <0x15000 0x400>;
    104			fifo-depth = <1024>;
    105			card-detect-delay = <200>;
    106			clocks = <&apbclk>, <&mmcclk>;
    107			clock-names = "biu", "ciu";
    108			interrupts = <7>;
    109			bus-width = <4>;
    110		};
    111	};
    112
    113	/*
    114	 * Embedded Vision subsystem UIO mappings; only relevant for EV VDK
    115	 *
    116	 * This node is intentionally put outside of MB above becase
    117	 * it maps areas outside of MB's 0xez-0xfz.
    118	 */
    119	uio_ev: uio@d0000000 {
    120		compatible = "generic-uio";
    121		reg = <0xd0000000 0x2000 0xd1000000 0x2000 0x90000000 0x10000000 0xc0000000 0x10000000>;
    122		reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem";
    123		interrupt-parent = <&mb_intc>;
    124		interrupts = <23>;
    125	};
    126};