cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intc-compact.c (4747B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
      4 */
      5
      6#include <linux/interrupt.h>
      7#include <linux/module.h>
      8#include <linux/of.h>
      9#include <linux/irqdomain.h>
     10#include <linux/irqchip.h>
     11#include <asm/irq.h>
     12
     13#define NR_CPU_IRQS	32	/* number of irq lines coming in */
     14#define TIMER0_IRQ	3	/* Fixed by ISA */
     15
     16/*
     17 * Early Hardware specific Interrupt setup
     18 * -Platform independent, needed for each CPU (not foldable into init_IRQ)
     19 * -Called very early (start_kernel -> setup_arch -> setup_processor)
     20 *
     21 * what it does ?
     22 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
     23 */
     24void arc_init_IRQ(void)
     25{
     26	unsigned int level_mask = 0, i;
     27
     28       /* Is timer high priority Interrupt (Level2 in ARCompact jargon) */
     29	level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;
     30
     31	/*
     32	 * Write to register, even if no LV2 IRQs configured to reset it
     33	 * in case bootloader had mucked with it
     34	 */
     35	write_aux_reg(AUX_IRQ_LEV, level_mask);
     36
     37	if (level_mask)
     38		pr_info("Level-2 interrupts bitset %x\n", level_mask);
     39
     40	/*
     41	 * Disable all IRQ lines so faulty external hardware won't
     42	 * trigger interrupt that kernel is not ready to handle.
     43	 */
     44	for (i = TIMER0_IRQ; i < NR_CPU_IRQS; i++) {
     45		unsigned int ienb;
     46
     47		ienb = read_aux_reg(AUX_IENABLE);
     48		ienb &= ~(1 << i);
     49		write_aux_reg(AUX_IENABLE, ienb);
     50	}
     51}
     52
     53/*
     54 * ARC700 core includes a simple on-chip intc supporting
     55 * -per IRQ enable/disable
     56 * -2 levels of interrupts (high/low)
     57 * -all interrupts being level triggered
     58 *
     59 * To reduce platform code, we assume all IRQs directly hooked-up into intc.
     60 * Platforms with external intc, hence cascaded IRQs, are free to over-ride
     61 * below, per IRQ.
     62 */
     63
     64static void arc_irq_mask(struct irq_data *data)
     65{
     66	unsigned int ienb;
     67
     68	ienb = read_aux_reg(AUX_IENABLE);
     69	ienb &= ~(1 << data->hwirq);
     70	write_aux_reg(AUX_IENABLE, ienb);
     71}
     72
     73static void arc_irq_unmask(struct irq_data *data)
     74{
     75	unsigned int ienb;
     76
     77	ienb = read_aux_reg(AUX_IENABLE);
     78	ienb |= (1 << data->hwirq);
     79	write_aux_reg(AUX_IENABLE, ienb);
     80}
     81
     82static struct irq_chip onchip_intc = {
     83	.name           = "ARC In-core Intc",
     84	.irq_mask	= arc_irq_mask,
     85	.irq_unmask	= arc_irq_unmask,
     86};
     87
     88static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
     89			       irq_hw_number_t hw)
     90{
     91	switch (hw) {
     92	case TIMER0_IRQ:
     93		irq_set_percpu_devid(irq);
     94		irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
     95		break;
     96	default:
     97		irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
     98	}
     99	return 0;
    100}
    101
    102static const struct irq_domain_ops arc_intc_domain_ops = {
    103	.xlate = irq_domain_xlate_onecell,
    104	.map = arc_intc_domain_map,
    105};
    106
    107static int __init
    108init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
    109{
    110	struct irq_domain *root_domain;
    111
    112	if (parent)
    113		panic("DeviceTree incore intc not a root irq controller\n");
    114
    115	root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS,
    116					    &arc_intc_domain_ops, NULL);
    117	if (!root_domain)
    118		panic("root irq domain not avail\n");
    119
    120	/*
    121	 * Needed for primary domain lookup to succeed
    122	 * This is a primary irqchip, and can never have a parent
    123	 */
    124	irq_set_default_host(root_domain);
    125
    126	return 0;
    127}
    128
    129IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
    130
    131/*
    132 * arch_local_irq_enable - Enable interrupts.
    133 *
    134 * 1. Explicitly called to re-enable interrupts
    135 * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
    136 *    which maybe in hard ISR itself
    137 *
    138 * Semantics of this function change depending on where it is called from:
    139 *
    140 * -If called from hard-ISR, it must not invert interrupt priorities
    141 *  e.g. suppose TIMER is high priority (Level 2) IRQ
    142 *    Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
    143 *    Here local_irq_enable( ) shd not re-enable lower priority interrupts
    144 * -If called from soft-ISR, it must re-enable all interrupts
    145 *    soft ISR are low priority jobs which can be very slow, thus all IRQs
    146 *    must be enabled while they run.
    147 *    Now hardware context wise we may still be in L2 ISR (not done rtie)
    148 *    still we must re-enable both L1 and L2 IRQs
    149 *  Another twist is prev scenario with flow being
    150 *     L1 ISR ==> interrupted by L2 ISR  ==> L2 soft ISR
    151 *     here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
    152 *     over-written (this is deficiency in ARC700 Interrupt mechanism)
    153 */
    154
    155#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS	/* Complex version for 2 IRQ levels */
    156
    157void arch_local_irq_enable(void)
    158{
    159	unsigned long flags = arch_local_save_flags();
    160
    161	if (flags & STATUS_A2_MASK)
    162		flags |= STATUS_E2_MASK;
    163	else if (flags & STATUS_A1_MASK)
    164		flags |= STATUS_E1_MASK;
    165
    166	arch_local_irq_restore(flags);
    167}
    168
    169EXPORT_SYMBOL(arch_local_irq_enable);
    170#endif