cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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Kconfig-nommu (2097B)


      1# SPDX-License-Identifier: GPL-2.0
      2#
      3# Kconfig for uClinux(non-paged MM) depend configurations
      4# Hyok S. Choi <hyok.choi@samsung.com>
      5# 
      6
      7config SET_MEM_PARAM
      8	bool "Set flash/sdram size and base addr"
      9	help
     10	 Say Y to manually set the base addresses and sizes.
     11	 otherwise, the default values are assigned.
     12
     13config DRAM_BASE
     14	hex '(S)DRAM Base Address' if SET_MEM_PARAM
     15	default 0x00800000
     16
     17config DRAM_SIZE
     18	hex '(S)DRAM SIZE' if SET_MEM_PARAM
     19	default 0x00800000
     20
     21config FLASH_MEM_BASE
     22	hex 'FLASH Base Address' if SET_MEM_PARAM
     23	depends on CPU_ARM740T || CPU_ARM946E || CPU_ARM940T
     24	default 0x00400000
     25
     26config FLASH_SIZE
     27	hex 'FLASH Size' if SET_MEM_PARAM
     28	depends on CPU_ARM740T || CPU_ARM946E || CPU_ARM940T
     29	default 0x00400000
     30
     31config PROCESSOR_ID
     32	hex 'Hard wire the processor ID'
     33	default 0x00007700
     34	depends on !(CPU_CP15 || CPU_V7M)
     35	help
     36	  If processor has no CP15 register, this processor ID is
     37	  used instead of the auto-probing which utilizes the register.
     38
     39config REMAP_VECTORS_TO_RAM
     40	bool 'Install vectors to the beginning of RAM'
     41	help
     42	  The kernel needs to change the hardware exception vectors.
     43	  In nommu mode, the hardware exception vectors are normally
     44	  placed at address 0x00000000. However, this region may be
     45	  occupied by read-only memory depending on H/W design.
     46
     47	  If the region contains read-write memory, say 'n' here.
     48
     49	  If your CPU provides a remap facility which allows the exception
     50	  vectors to be mapped to writable memory, say 'n' here.
     51
     52	  Otherwise, say 'y' here.  In this case, the kernel will require
     53	  external support to redirect the hardware exception vectors to
     54	  the writable versions located at DRAM_BASE.
     55
     56config ARM_MPU
     57       bool 'Use the ARM v7 PMSA Compliant MPU'
     58       depends on CPU_V7 || CPU_V7M
     59       default y if CPU_V7
     60       help
     61         Some ARM systems without an MMU have instead a Memory Protection
     62         Unit (MPU) that defines the type and permissions for regions of
     63         memory.
     64
     65         If your CPU has an MPU then you should choose 'y' here unless you
     66         know that you do not want to use the MPU.