cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

am335x-baltos-ir2110.dts (1915B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
      4 */
      5
      6/*
      7 * VScom OnRISC
      8 * http://www.vscom.de
      9 */
     10
     11/dts-v1/;
     12
     13#include "am335x-baltos.dtsi"
     14#include "am335x-baltos-leds.dtsi"
     15
     16/ {
     17	model = "OnRISC Baltos iR 2110";
     18};
     19
     20&am33xx_pinmux {
     21	uart1_pins: pinmux_uart1_pins {
     22		pinctrl-single,pins = <
     23			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
     24			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0)
     25			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
     26			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
     27			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
     28			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
     29			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
     30			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
     31		>;
     32	};
     33
     34	mmc1_pins: pinmux_mmc1_pins {
     35		pinctrl-single,pins = <
     36			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE7)     /* MMC1 CD */
     37		>;
     38	};
     39};
     40
     41&uart1 {
     42	pinctrl-names = "default";
     43	pinctrl-0 = <&uart1_pins>;
     44	dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
     45	dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
     46	dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
     47	rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
     48
     49	status = "okay";
     50};
     51
     52&usb0_phy {
     53	status = "okay";
     54};
     55
     56&usb0 {
     57	status = "okay";
     58	dr_mode = "host";
     59};
     60
     61&davinci_mdio_sw {
     62	phy0: ethernet-phy@0 {
     63		reg = <1>;
     64	};
     65};
     66
     67&cpsw_port1 {
     68	phy-mode = "rmii";
     69	ti,dual-emac-pvid = <1>;
     70	phy-handle = <&phy0>;
     71};
     72
     73&cpsw_port2 {
     74	phy-mode = "rgmii-id";
     75	ti,dual-emac-pvid = <2>;
     76	phy-handle = <&phy1>;
     77};
     78
     79&mmc1 {
     80	pinctrl-names = "default";
     81	pinctrl-0 = <&mmc1_pins>;
     82	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
     83};