cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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am335x-baltos-ir5221.dts (4058B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
      4 */
      5
      6/*
      7 * VScom OnRISC
      8 * http://www.vscom.de
      9 */
     10
     11/dts-v1/;
     12
     13#include "am335x-baltos.dtsi"
     14#include "am335x-baltos-leds.dtsi"
     15
     16/ {
     17	model = "OnRISC Baltos iR 5221";
     18};
     19
     20&am33xx_pinmux {
     21	tca6416_pins: pinmux_tca6416_pins {
     22		pinctrl-single,pins = <
     23			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7)      /* xdma_event_intr1.gpio0[20] tca6416 stuff */
     24		>;
     25	};
     26
     27
     28	dcan1_pins: pinmux_dcan1_pins {
     29		pinctrl-single,pins = <
     30			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2)      /* uart0_ctsn.dcan1_tx_mux0 */
     31			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2)      /* uart0_rtsn.dcan1_rx_mux0 */
     32		>;
     33	};
     34
     35	uart1_pins: pinmux_uart1_pins {
     36		pinctrl-single,pins = <
     37			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
     38			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0)
     39			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
     40			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
     41			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
     42			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
     43			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
     44			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
     45		>;
     46	};
     47
     48	uart2_pins: pinmux_uart2_pins {
     49		pinctrl-single,pins = <
     50			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)      /* spi0_sclk.uart2_rxd_mux3 */
     51			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)      /* spi0_d0.uart2_txd_mux3 */
     52			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* i2c0_sda.uart2_ctsn_mux0 */
     53			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* i2c0_scl.uart2_rtsn_mux0 */
     54			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad12.gpio1[12] DTR */
     55			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad13.gpio1[13] DSR */
     56			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad14.gpio1[14] DCD */
     57			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad15.gpio1[15] RI */
     58
     59			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7)      /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
     60		>;
     61	};
     62
     63	mmc1_pins: pinmux_mmc1_pins {
     64		pinctrl-single,pins = <
     65			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7)     /* MMC1 CD */
     66		>;
     67	};
     68};
     69
     70&uart1 {
     71	pinctrl-names = "default";
     72	pinctrl-0 = <&uart1_pins>;
     73	dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
     74	dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
     75	dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
     76	rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
     77
     78	status = "okay";
     79};
     80
     81&uart2 {
     82	pinctrl-names = "default";
     83	pinctrl-0 = <&uart2_pins>;
     84	dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
     85	dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
     86	dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
     87	rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
     88
     89	status = "okay";
     90};
     91
     92&i2c1 {
     93	tca6416: gpio@20 {
     94		compatible = "ti,tca6416";
     95		reg = <0x20>;
     96		gpio-controller;
     97		#gpio-cells = <2>;
     98		interrupt-parent = <&gpio0>;
     99		interrupts = <20 IRQ_TYPE_EDGE_RISING>;
    100		pinctrl-names = "default";
    101		pinctrl-0 = <&tca6416_pins>;
    102	};
    103};
    104
    105&usb0_phy {
    106	status = "okay";
    107};
    108
    109&usb1_phy {
    110	status = "okay";
    111};
    112
    113&usb0 {
    114	status = "okay";
    115	dr_mode = "host";
    116};
    117
    118&usb1 {
    119	status = "okay";
    120	dr_mode = "host";
    121};
    122
    123&cpsw_port1 {
    124	phy-mode = "rmii";
    125	ti,dual-emac-pvid = <1>;
    126	fixed-link {
    127		speed = <100>;
    128		full-duplex;
    129	};
    130};
    131
    132&cpsw_port2 {
    133	phy-mode = "rgmii-id";
    134	ti,dual-emac-pvid = <2>;
    135	phy-handle = <&phy1>;
    136};
    137
    138&dcan1 {
    139	pinctrl-names = "default";
    140	pinctrl-0 = <&dcan1_pins>;
    141
    142	status = "okay";
    143};
    144
    145&mmc1 {
    146	pinctrl-names = "default";
    147	pinctrl-0 = <&mmc1_pins>;
    148	cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
    149};