cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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am335x-moxa-uc-8100-me-t.dts (1938B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2017 MOXA Inc. - https://www.moxa.com/
      4 *
      5 * Author: SZ Lin (林上智) <sz.lin@moxa.com>
      6 */
      7/dts-v1/;
      8
      9#include "am335x-moxa-uc-8100-common.dtsi"
     10
     11/ {
     12	model = "Moxa UC-8100-ME-T";
     13	compatible = "moxa,uc-8100-me-t", "ti,am33xx";
     14
     15	memory {
     16		device_type = "memory";
     17		reg = <0x80000000 0x20000000>; /* 512 MB */
     18	};
     19
     20	leds {
     21		compatible = "gpio-leds";
     22		led1 {
     23			label = "uc8100me:CEL1";
     24			gpios = <&gpio_xten 8 0>;
     25			default-state = "off";
     26		};
     27
     28		led2 {
     29			label = "uc8100me:CEL2";
     30			gpios = <&gpio_xten 9 0>;
     31			default-state = "off";
     32		};
     33
     34		led3 {
     35			label = "uc8100me:CEL3";
     36			gpios = <&gpio_xten 10 0>;
     37			default-state = "off";
     38		};
     39
     40		led4 {
     41			label = "uc8100me:DIA1";
     42			gpios = <&gpio_xten 11 0>;
     43			default-state = "off";
     44		};
     45		led5 {
     46			label = "uc8100me:DIA2";
     47			gpios = <&gpio_xten 12 0>;
     48			default-state = "off";
     49		};
     50		led6 {
     51			label = "uc8100me:DIA3";
     52			gpios = <&gpio_xten 13 0>;
     53			default-state = "off";
     54		};
     55		led7 {
     56			label = "uc8100me:SD";
     57			gpios = <&gpio_xten 14 0>;
     58			default-state = "off";
     59		};
     60		led8 {
     61			label = "uc8100me:USB";
     62			gpios = <&gpio_xten 15 0>;
     63			default-state = "off";
     64		};
     65		led9 {
     66			label = "uc8100me:USER";
     67			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
     68			default-state = "off";
     69		};
     70	};
     71};
     72
     73&i2c0 {
     74	tpm: tpm@20 {
     75		compatible = "infineon,slb9645tt";
     76		reg = <0x20>;
     77	};
     78};
     79
     80&tps {
     81	regulators {
     82		vdd1_reg: regulator@2 {
     83			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
     84			regulator-name = "vdd_mpu";
     85			regulator-min-microvolt = <912500>;
     86			regulator-max-microvolt = <1378000>;
     87			regulator-boot-on;
     88			regulator-always-on;
     89		};
     90
     91		vdd2_reg: regulator@3 {
     92			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
     93			regulator-name = "vdd_core";
     94			regulator-min-microvolt = <912500>;
     95			regulator-max-microvolt = <1150000>;
     96			regulator-boot-on;
     97			regulator-always-on;
     98		};
     99	};
    100};
    101