cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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am335x-netcan-plus-1xx.dts (1527B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
      4 */
      5
      6/*
      7 * VScom OnRISC
      8 * http://www.vscom.de
      9 */
     10
     11/dts-v1/;
     12
     13#include "am335x-baltos.dtsi"
     14#include "am335x-baltos-leds.dtsi"
     15
     16/ {
     17	model = "NetCAN";
     18
     19	leds {
     20		pinctrl-names = "default";
     21		pinctrl-0 = <&user_leds_s0>;
     22
     23		compatible = "gpio-leds";
     24
     25		led@1 {
     26			label = "can_data";
     27			linux,default-trigger = "netdev";
     28			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
     29			default-state = "off";
     30		};
     31		led@2 {
     32			label = "can_error";
     33			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
     34			default-state = "off";
     35		};
     36	};
     37};
     38
     39&am33xx_pinmux {
     40	user_leds_s0: user_leds_s0 {
     41		pinctrl-single,pins = <
     42			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* CAN Data LED */
     43			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* CAN Error LED */
     44		>;
     45	};
     46
     47	dcan1_pins: pinmux_dcan1_pins {
     48		pinctrl-single,pins = <
     49			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2)	/* CAN TX */
     50			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2)	/* CAN RX */
     51		>;
     52	};
     53};
     54
     55&usb0_phy {
     56	status = "okay";
     57};
     58
     59&usb0 {
     60	status = "okay";
     61	dr_mode = "host";
     62};
     63
     64&davinci_mdio_sw {
     65	phy0: ethernet-phy@0 {
     66		reg = <1>;
     67	};
     68};
     69
     70&cpsw_port1 {
     71	phy-mode = "rmii";
     72	ti,dual-emac-pvid = <1>;
     73	phy-handle = <&phy0>;
     74};
     75
     76&cpsw_port2 {
     77	phy-mode = "rgmii-id";
     78	ti,dual-emac-pvid = <2>;
     79	phy-handle = <&phy1>;
     80};
     81
     82&dcan1 {
     83	pinctrl-names = "default";
     84	pinctrl-0 = <&dcan1_pins>;
     85
     86	status = "okay";
     87};