am335x-osd3358-sm-red.dts (13211B)
1//SPDX-License-Identifier: GPL-2.0 2/* Copyright (C) 2018 Octavo Systems LLC - https://www.octavosystems.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/dts-v1/; 10 11#include "am33xx.dtsi" 12#include "am335x-osd335x-common.dtsi" 13#include <dt-bindings/interrupt-controller/irq.h> 14 15#include <dt-bindings/display/tda998x.h> 16 17/ { 18 model = "Octavo Systems OSD3358-SM-RED"; 19 compatible = "oct,osd3358-sm-refdesign", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; 20}; 21 22&ldo3_reg { 23 regulator-min-microvolt = <1800000>; 24 regulator-max-microvolt = <1800000>; 25 regulator-always-on; 26}; 27 28&mmc2 { 29 vmmc-supply = <&vmmcsd_fixed>; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&emmc_pins>; 32 bus-width = <8>; 33 status = "okay"; 34}; 35 36&lcdc { 37 status = "okay"; 38 39 /* If you want to get 24 bit RGB and 16 BGR mode instead of 40 * current 16 bit RGB and 24 BGR modes, set the propety 41 * below to "crossed" and uncomment the video-ports -property 42 * in tda19988 node. 43 * AM335x errata for wiring: 44 * https://www.ti.com/lit/er/sprz360i/sprz360i.pdf 45 */ 46 47 blue-and-red-wiring = "straight"; 48 49 port { 50 lcdc_0: endpoint { 51 remote-endpoint = <&hdmi_0>; 52 }; 53 }; 54}; 55 56&i2c0 { 57 tda19988: hdmi-encoder@70 { 58 compatible = "nxp,tda998x"; 59 reg = <0x70>; 60 61 pinctrl-names = "default", "off"; 62 pinctrl-0 = <&nxp_hdmi_bonelt_pins>; 63 pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; 64 65 /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ 66 /* video-ports = <0x234501>; */ 67 68 #sound-dai-cells = <0>; 69 audio-ports = < TDA998x_I2S 0x03>; 70 71 port { 72 hdmi_0: endpoint { 73 remote-endpoint = <&lcdc_0>; 74 }; 75 }; 76 }; 77 78 mpu9250: imu@68 { 79 compatible = "invensense,mpu6050"; 80 reg = <0x68>; 81 interrupt-parent = <&gpio3>; 82 interrupts = <21 IRQ_TYPE_EDGE_RISING>; 83 i2c-gate { 84 #address-cells = <1>; 85 #size-cells = <0>; 86 ax8975@c { 87 compatible = "asahi-kasei,ak8975"; 88 reg = <0x0c>; 89 }; 90 }; 91 /*invensense,int_config = <0x10>; 92 invensense,level_shifter = <0>; 93 invensense,orientation = [01 00 00 00 01 00 00 00 01]; 94 invensense,sec_slave_type = <0>; 95 invensense,key = [4e cc 7e eb f6 1e 35 22 00 34 0d 65 32 e9 94 89];*/ 96 }; 97 98 bmp280: pressure@76 { 99 compatible = "bosch,bmp280"; 100 reg = <0x76>; 101 }; 102}; 103 104&mcasp0 { 105 #sound-dai-cells = <0>; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&mcasp0_pins>; 108 status = "okay"; 109 op-mode = <0>; /* MCASP_IIS_MODE */ 110 tdm-slots = <2>; 111 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 112 0 0 1 0 113 >; 114 tx-num-evt = <32>; 115 rx-num-evt = <32>; 116}; 117 118/ { 119 clk_mcasp0_fixed: clk-mcasp0-fixed { 120 #clock-cells = <0>; 121 compatible = "fixed-clock"; 122 clock-frequency = <24576000>; 123 }; 124 125 clk_mcasp0: clk-mcasp0 { 126 #clock-cells = <0>; 127 compatible = "gpio-gate-clock"; 128 clocks = <&clk_mcasp0_fixed>; 129 enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ 130 }; 131 132 sound { 133 compatible = "simple-audio-card"; 134 simple-audio-card,name = "TI BeagleBone Black"; 135 simple-audio-card,format = "i2s"; 136 simple-audio-card,bitclock-master = <&dailink0_master>; 137 simple-audio-card,frame-master = <&dailink0_master>; 138 139 dailink0_master: simple-audio-card,cpu { 140 sound-dai = <&mcasp0>; 141 clocks = <&clk_mcasp0>; 142 }; 143 144 simple-audio-card,codec { 145 sound-dai = <&tda19988>; 146 }; 147 }; 148 149 chosen { 150 stdout-path = &uart0; 151 }; 152 153 leds { 154 pinctrl-names = "default"; 155 pinctrl-0 = <&user_leds_s0>; 156 157 compatible = "gpio-leds"; 158 159 led2 { 160 label = "beaglebone:green:usr0"; 161 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 162 linux,default-trigger = "heartbeat"; 163 default-state = "off"; 164 }; 165 166 led3 { 167 label = "beaglebone:green:usr1"; 168 gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; 169 linux,default-trigger = "mmc0"; 170 default-state = "off"; 171 }; 172 173 led4 { 174 label = "beaglebone:green:usr2"; 175 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; 176 linux,default-trigger = "cpu0"; 177 default-state = "off"; 178 }; 179 180 led5 { 181 label = "beaglebone:green:usr3"; 182 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; 183 linux,default-trigger = "mmc1"; 184 default-state = "off"; 185 }; 186 }; 187 188 vmmcsd_fixed: fixedregulator0 { 189 compatible = "regulator-fixed"; 190 regulator-name = "vmmcsd_fixed"; 191 regulator-min-microvolt = <3300000>; 192 regulator-max-microvolt = <3300000>; 193 }; 194}; 195 196&am33xx_pinmux { 197 pinctrl-names = "default"; 198 pinctrl-0 = <&clkout2_pin>; 199 200 nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { 201 pinctrl-single,pins = < 202 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) 203 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) 204 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) 205 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) 206 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) 207 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) 208 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) 209 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) 210 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) 211 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) 212 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) 213 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) 214 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) 215 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) 216 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) 217 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) 218 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) 219 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 220 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 221 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 222 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 223 >; 224 }; 225 226 nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { 227 pinctrl-single,pins = < 228 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) 229 >; 230 }; 231 232 mcasp0_pins: mcasp0-pins { 233 pinctrl-single,pins = < 234 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) 235 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ 236 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) 237 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 238 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ 239 >; 240 }; 241 242 flash_enable: flash-enable { 243 pinctrl-single,pins = < 244 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ 245 >; 246 }; 247 248 imu_interrupt: imu-interrupt { 249 pinctrl-single,pins = < 250 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ 251 >; 252 }; 253 254 ethernet_interrupt: ethernet-interrupt{ 255 pinctrl-single,pins = < 256 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ 257 >; 258 }; 259 260 user_leds_s0: user-leds-s0 { 261 pinctrl-single,pins = < 262 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ 263 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ 264 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ 265 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ 266 >; 267 }; 268 269 i2c2_pins: pinmux-i2c2-pins { 270 pinctrl-single,pins = < 271 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ 272 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ 273 >; 274 }; 275 276 uart0_pins: pinmux-uart0-pins { 277 pinctrl-single,pins = < 278 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 279 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 280 >; 281 }; 282 283 clkout2_pin: pinmux-clkout2-pin { 284 pinctrl-single,pins = < 285 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ 286 >; 287 }; 288 289 cpsw_default: cpsw-default { 290 pinctrl-single,pins = < 291 /* Slave 1 */ 292 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 293 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 294 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 295 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 296 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 297 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 298 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 299 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) 300 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) 301 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) 302 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) 303 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) 304 >; 305 }; 306 307 cpsw_sleep: cpsw-sleep { 308 pinctrl-single,pins = < 309 /* Slave 1 reset value */ 310 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) 311 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) 312 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 313 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 314 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 315 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 316 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 317 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 318 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 319 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 320 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 321 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 322 >; 323 }; 324 325 davinci_mdio_default: davinci-mdio-default { 326 pinctrl-single,pins = < 327 /* MDIO */ 328 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) 329 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) 330 >; 331 }; 332 333 davinci_mdio_sleep: davinci-mdio-sleep { 334 pinctrl-single,pins = < 335 /* MDIO reset value */ 336 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) 337 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) 338 >; 339 }; 340 341 mmc1_pins: pinmux-mmc1-pins { 342 pinctrl-single,pins = < 343 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ 344 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) 345 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) 346 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) 347 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) 348 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) 349 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 350 >; 351 }; 352 353 emmc_pins: pinmux-emmc-pins { 354 pinctrl-single,pins = < 355 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ 356 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ 357 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ 358 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ 359 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ 360 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ 361 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ 362 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ 363 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ 364 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ 365 >; 366 }; 367}; 368 369 370&uart0 { 371 pinctrl-names = "default"; 372 pinctrl-0 = <&uart0_pins>; 373 374 status = "okay"; 375}; 376 377&usb0 { 378 dr_mode = "peripheral"; 379 interrupts-extended = <&intc 18 &tps 0>; 380 interrupt-names = "mc", "vbus"; 381}; 382 383&usb1 { 384 dr_mode = "host"; 385}; 386 387&i2c2 { 388 pinctrl-names = "default"; 389 pinctrl-0 = <&i2c2_pins>; 390 status = "okay"; 391 clock-frequency = <100000>; 392}; 393 394&cpsw_port1 { 395 phy-handle = <ðphy0>; 396 phy-mode = "rgmii-txid"; 397 ti,dual-emac-pvid = <1>; 398}; 399 400&cpsw_port2 { 401 status = "disabled"; 402}; 403 404&mac_sw { 405 pinctrl-names = "default", "sleep"; 406 pinctrl-0 = <&cpsw_default>; 407 pinctrl-1 = <&cpsw_sleep>; 408 status = "okay"; 409}; 410 411&davinci_mdio_sw { 412 pinctrl-names = "default", "sleep"; 413 pinctrl-0 = <&davinci_mdio_default>; 414 pinctrl-1 = <&davinci_mdio_sleep>; 415 416 ethphy0: ethernet-phy@4 { 417 reg = <4>; 418 }; 419}; 420 421&mmc1 { 422 status = "okay"; 423 vmmc-supply = <&vmmcsd_fixed>; 424 bus-width = <0x4>; 425 pinctrl-names = "default"; 426 pinctrl-0 = <&mmc1_pins>; 427 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 428}; 429 430&rtc { 431 system-power-controller; 432 clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 433 clock-names = "ext-clk", "int-clk"; 434};