cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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am335x-regor.dtsi (6031B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Copyright (C) 2019 Phytec Messtechnik GmbH
      4 * Author: Teresa Remmet <t.remmet@phytec.de>
      5 *
      6 */
      7
      8/ {
      9	model = "Phytec AM335x phyBOARD-REGOR";
     10	compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx";
     11
     12	vcc3v3: fixedregulator@1 {
     13		compatible = "regulator-fixed";
     14		regulator-name = "vcc3v3";
     15		regulator-min-microvolt = <3300000>;
     16		regulator-max-microvolt = <3300000>;
     17		regulator-boot-on;
     18	};
     19
     20	/* User IO */
     21	user_leds: user_leds {
     22		compatible = "gpio-leds";
     23		pinctrl-names = "default";
     24		pinctrl-0 = <&user_leds_pins>;
     25
     26		run_stop-led {
     27			gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
     28			linux,default-trigger = "gpio";
     29			default-state = "off";
     30		};
     31
     32		error-led {
     33			gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
     34			linux,default-trigger = "gpio";
     35			default-state = "off";
     36		};
     37	};
     38};
     39
     40/* User Leds */
     41&am33xx_pinmux {
     42	user_leds_pins: pinmux_user_leds {
     43		pinctrl-single,pins = <
     44			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* lcd_hsync.gpio2_22 */
     45			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* mcasp0_fsx.gpio3_15 */
     46		>;
     47	};
     48};
     49
     50/* CAN Busses */
     51&am33xx_pinmux {
     52	dcan1_pins: pinmux_dcan1 {
     53		pinctrl-single,pins = <
     54			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2)	/* uart0_ctsn.d_can1_tx */
     55			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2)	/* uart0_rtsn.d_can1_rx */
     56		>;
     57	};
     58};
     59
     60&dcan1 {
     61	pinctrl-names = "default";
     62	pinctrl-0 = <&dcan1_pins>;
     63	status = "okay";
     64};
     65
     66/* Ethernet */
     67&am33xx_pinmux {
     68	ethernet1_pins: pinmux_ethernet1 {
     69		pinctrl-single,pins = <
     70			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a0.mii2_txen */
     71			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a1.mii2_rxdv */
     72			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a2.mii2_txd3 */
     73			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a3.mii2_txd2 */
     74			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a4.mii2_txd1 */
     75			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a5.mii2_txd0 */
     76			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a6.mii2_txclk */
     77			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a7.mii2_rxclk */
     78			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a8.mii2_rxd3 */
     79			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1)	 /* gpmc_a9.mii2_rxd2 */
     80			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a10.mii2_rxd1 */
     81			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a11.mii2_rxd0 */
     82			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_wpn.mii2_rxerr */
     83			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_ben1.mii2_col */
     84		>;
     85	};
     86};
     87
     88&cpsw_port2 {
     89	status = "okay";
     90	phy-handle = <&phy1>;
     91	phy-mode = "mii";
     92	ti,dual-emac-pvid = <2>;
     93};
     94
     95&davinci_mdio_sw {
     96	phy1: ethernet-phy@1 {
     97		reg = <1>;
     98	};
     99};
    100
    101&mac_sw {
    102	pinctrl-names = "default";
    103	pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
    104};
    105
    106/* GPIOs */
    107&am33xx_pinmux {
    108	pinctrl-names = "default";
    109	pinctrl-0 = <&user_gpios_pins>;
    110
    111	user_gpios_pins: pinmux_user_gpios {
    112		pinctrl-single,pins = <
    113			/* DIGIN 1-4 */
    114			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7)		/* gpmc_ad11.gpio0_27 */
    115			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7)		/* gpmc_ad10.gpio0_26 */
    116			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7)		/* gpmc_ad9.gpio0_23 */
    117			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7)		/* gpmc_ad8.gpio0_22 */
    118			/* DIGOUT 1-4 */
    119			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7)		/* gpmc_ad15.gpio1_15 */
    120			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7)		/* gpmc_ad14.gpio1_14 */
    121			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7)		/* gpmc_ad13.gpio1_13 */
    122			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7)		/* gpmc_ad12.gpio1_12 */
    123		>;
    124	};
    125};
    126
    127/* MMC */
    128&am33xx_pinmux {
    129	mmc1_pins: pinmux_mmc1 {
    130		pinctrl-single,pins = <
    131			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
    132			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
    133			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
    134			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
    135			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
    136			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
    137			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7)	/* spi0_cs1.mmc0_sdcd */
    138		>;
    139	};
    140};
    141
    142&mmc1 {
    143	vmmc-supply = <&vcc3v3>;
    144	bus-width = <4>;
    145	pinctrl-names = "default";
    146	pinctrl-0 = <&mmc1_pins>;
    147	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
    148	status = "okay";
    149};
    150
    151/* RTC */
    152&i2c_rtc {
    153	status = "okay";
    154};
    155
    156/* UARTs */
    157&am33xx_pinmux {
    158	uart0_pins: pinmux_uart0 {
    159		pinctrl-single,pins = <
    160			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
    161			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
    162		>;
    163	};
    164
    165	uart2_pins: pinmux_uart2 {
    166		pinctrl-single,pins = <
    167			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_tx_clk.uart2_rxd */
    168			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_rx_clk.uart2_txd */
    169		>;
    170	};
    171};
    172
    173&uart0 {
    174	pinctrl-names = "default";
    175	pinctrl-0 = <&uart0_pins>;
    176	status = "okay";
    177};
    178
    179&uart2 {
    180	pinctrl-names = "default";
    181	pinctrl-0 = <&uart2_pins>;
    182	status = "okay";
    183};
    184
    185/* RS485 - UART1 */
    186&am33xx_pinmux {
    187	uart1_rs485_pins: pinmux_uart1_rs485_pins {
    188		pinctrl-single,pins = <
    189			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
    190			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
    191			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0)
    192		>;
    193	};
    194};
    195
    196&uart1 {
    197	pinctrl-names = "default";
    198	pinctrl-0 = <&uart1_rs485_pins>;
    199	status = "okay";
    200	linux,rs485-enabled-at-boot-time;
    201};