cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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am35xx-clocks.dtsi (3245B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Device Tree Source for OMAP3 clock data
      4 *
      5 * Copyright (C) 2013 Texas Instruments, Inc.
      6 */
      7&scm_clocks {
      8	emac_ick: emac_ick@32c {
      9		#clock-cells = <0>;
     10		compatible = "ti,am35xx-gate-clock";
     11		clocks = <&ipss_ick>;
     12		reg = <0x032c>;
     13		ti,bit-shift = <1>;
     14	};
     15
     16	emac_fck: emac_fck@32c {
     17		#clock-cells = <0>;
     18		compatible = "ti,gate-clock";
     19		clocks = <&rmii_ck>;
     20		reg = <0x032c>;
     21		ti,bit-shift = <9>;
     22	};
     23
     24	vpfe_ick: vpfe_ick@32c {
     25		#clock-cells = <0>;
     26		compatible = "ti,am35xx-gate-clock";
     27		clocks = <&ipss_ick>;
     28		reg = <0x032c>;
     29		ti,bit-shift = <2>;
     30	};
     31
     32	vpfe_fck: vpfe_fck@32c {
     33		#clock-cells = <0>;
     34		compatible = "ti,gate-clock";
     35		clocks = <&pclk_ck>;
     36		reg = <0x032c>;
     37		ti,bit-shift = <10>;
     38	};
     39
     40	hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c {
     41		#clock-cells = <0>;
     42		compatible = "ti,am35xx-gate-clock";
     43		clocks = <&ipss_ick>;
     44		reg = <0x032c>;
     45		ti,bit-shift = <0>;
     46	};
     47
     48	hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c {
     49		#clock-cells = <0>;
     50		compatible = "ti,gate-clock";
     51		clocks = <&sys_ck>;
     52		reg = <0x032c>;
     53		ti,bit-shift = <8>;
     54	};
     55
     56	hecc_ck: hecc_ck@32c {
     57		#clock-cells = <0>;
     58		compatible = "ti,am35xx-gate-clock";
     59		clocks = <&sys_ck>;
     60		reg = <0x032c>;
     61		ti,bit-shift = <3>;
     62	};
     63};
     64&cm_clocks {
     65	clock@a10 {
     66		compatible = "ti,clksel";
     67		reg = <0xa10>;
     68		#clock-cells = <2>;
     69		#address-cells = <0>;
     70
     71		ipss_ick: clock-ipss-ick {
     72			#clock-cells = <0>;
     73			compatible = "ti,am35xx-interface-clock";
     74			clock-output-names = "ipss_ick";
     75			clocks = <&core_l3_ick>;
     76			ti,bit-shift = <4>;
     77		};
     78
     79		uart4_ick_am35xx: clock-uart4-ick-am35xx {
     80			#clock-cells = <0>;
     81			compatible = "ti,omap3-interface-clock";
     82			clock-output-names = "uart4_ick_am35xx";
     83			clocks = <&core_l4_ick>;
     84			ti,bit-shift = <23>;
     85		};
     86	};
     87
     88	rmii_ck: rmii_ck {
     89		#clock-cells = <0>;
     90		compatible = "fixed-clock";
     91		clock-frequency = <50000000>;
     92	};
     93
     94	pclk_ck: pclk_ck {
     95		#clock-cells = <0>;
     96		compatible = "fixed-clock";
     97		clock-frequency = <27000000>;
     98	};
     99
    100	clock@a00 {
    101		compatible = "ti,clksel";
    102		reg = <0xa00>;
    103		#clock-cells = <2>;
    104		#address-cells = <0>;
    105
    106		uart4_fck_am35xx: clock-uart4-fck-am35xx {
    107			#clock-cells = <0>;
    108			compatible = "ti,wait-gate-clock";
    109			clock-output-names = "uart4_fck_am35xx";
    110			clocks = <&core_48m_fck>;
    111			ti,bit-shift = <23>;
    112		};
    113	};
    114};
    115
    116&cm_clockdomains {
    117	core_l3_clkdm: core_l3_clkdm {
    118		compatible = "ti,clockdomain";
    119		clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
    120			 <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
    121			 <&hecc_ck>;
    122	};
    123
    124	core_l4_clkdm: core_l4_clkdm {
    125		compatible = "ti,clockdomain";
    126		clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
    127			 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
    128			 <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
    129			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
    130			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
    131			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
    132			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
    133			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
    134			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
    135			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
    136			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
    137			 <&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
    138	};
    139};