cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

arm-realview-eb-11mp-ctrevb.dts (2150B)

      1/*
      2 * Copyright 2016 Linaro Ltd
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a copy
      5 * of this software and associated documentation files (the "Software"), to deal
      6 * in the Software without restriction, including without limitation the rights
      7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
      8 * copies of the Software, and to permit persons to whom the Software is
      9 * furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     20 * THE SOFTWARE.
     21 */
     22
     23#include "arm-realview-eb-11mp.dts"
     24
     25/ {
     26	model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev B";
     27};
     28
     29/*
     30 * The revision B has a distinctly different layout of the syscon, so
     31 * append a specific compatible-string.
     32 */
     33&syscon {
     34	compatible = "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon", "simple-mfd";
     35};
     36
     37&intc {
     38	reg = <0x10101000 0x1000>,
     39	      <0x10100100 0x100>;
     40};
     41
     42&L2 {
     43	reg = <0x10102000 0x1000>;
     44};
     45
     46&scu {
     47	reg = <0x10100000 0x100>;
     48};
     49
     50&twd_timer {
     51	reg = <0x10100600 0x20>;
     52};
     53
     54&twd_wdog {
     55	reg = <0x10100620 0x20>;
     56};
     57
     58/*
     59 * On revision B, we cannot reach the secondary interrupt
     60 * controller, as a result, some peripherals that are dependent
     61 * on their IRQ cannot be reached, so disable them.
     62 */
     63&intc_second {
     64	status = "disabled";
     65};
     66
     67&gpio0 {
     68	status = "disabled";
     69};
     70
     71&gpio1 {
     72	status = "disabled";
     73};
     74
     75&gpio2 {
     76	status = "disabled";
     77};
     78
     79&serial2 {
     80	status = "disabled";
     81};
     82
     83&serial3 {
     84	status = "disabled";
     85};
     86
     87&ssp {
     88	status = "disabled";
     89};
     90
     91&wdog {
     92	status = "disabled";
     93};