cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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armada-370-mirabox.dts (3299B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Device Tree file for Globalscale Mirabox
      4 *
      5 * Gregory CLEMENT <gregory.clement@free-electrons.com>
      6 */
      7
      8/dts-v1/;
      9#include <dt-bindings/gpio/gpio.h>
     10#include "armada-370.dtsi"
     11
     12/ {
     13	model = "Globalscale Mirabox";
     14	compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
     15
     16	chosen {
     17		stdout-path = "serial0:115200n8";
     18	};
     19
     20	memory@0 {
     21		device_type = "memory";
     22		reg = <0x00000000 0x20000000>; /* 512 MB */
     23	};
     24
     25	soc {
     26		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
     27			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
     28			  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
     29
     30		internal-regs {
     31			serial@12000 {
     32				status = "okay";
     33			};
     34			timer@20300 {
     35				clock-frequency = <600000000>;
     36				status = "okay";
     37			};
     38
     39			gpio_leds {
     40				compatible = "gpio-leds";
     41				pinctrl-names = "default";
     42				pinctrl-0 = <&pwr_led_pin &stat_led_pins>;
     43
     44				green_pwr_led {
     45					label = "mirabox:green:pwr";
     46					gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
     47					default-state = "keep";
     48				};
     49
     50				blue_stat_led {
     51					label = "mirabox:blue:stat";
     52					gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
     53					default-state = "off";
     54				};
     55
     56				green_stat_led {
     57					label = "mirabox:green:stat";
     58					gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
     59					default-state = "off";
     60				};
     61			};
     62
     63			ethernet@70000 {
     64				pinctrl-0 = <&ge0_rgmii_pins>;
     65				pinctrl-names = "default";
     66				status = "okay";
     67				phy = <&phy0>;
     68				phy-mode = "rgmii-id";
     69			};
     70			ethernet@74000 {
     71				pinctrl-0 = <&ge1_rgmii_pins>;
     72				pinctrl-names = "default";
     73				status = "okay";
     74				phy = <&phy1>;
     75				phy-mode = "rgmii-id";
     76			};
     77
     78			crypto@90000 {
     79				status = "okay";
     80			};
     81
     82			mvsdio@d4000 {
     83				pinctrl-0 = <&sdio_pins3>;
     84				pinctrl-names = "default";
     85				status = "okay";
     86				/*
     87				 * No CD or WP GPIOs: SDIO interface used for
     88				 * Wifi/Bluetooth chip
     89				 */
     90				 broken-cd;
     91			};
     92
     93			usb@50000 {
     94				status = "okay";
     95			};
     96
     97			usb@51000 {
     98				status = "okay";
     99			};
    100
    101			i2c@11000 {
    102				status = "okay";
    103				clock-frequency = <100000>;
    104				pca9505: pca9505@25 {
    105					compatible = "nxp,pca9505";
    106					gpio-controller;
    107					#gpio-cells = <2>;
    108					reg = <0x25>;
    109				};
    110			};
    111		};
    112	};
    113};
    114
    115&pciec {
    116	status = "okay";
    117
    118	/* Internal mini-PCIe connector */
    119	pcie@1,0 {
    120		/* Port 0, Lane 0 */
    121		status = "okay";
    122	};
    123
    124	/* Connected on the PCB to a USB 3.0 XHCI controller */
    125	pcie@2,0 {
    126		/* Port 1, Lane 0 */
    127		status = "okay";
    128	};
    129};
    130
    131&mdio {
    132	pinctrl-0 = <&mdio_pins>;
    133	pinctrl-names = "default";
    134	phy0: ethernet-phy@0 {
    135		reg = <0>;
    136	};
    137
    138	phy1: ethernet-phy@1 {
    139		reg = <1>;
    140	};
    141};
    142
    143&pinctrl {
    144	pwr_led_pin: pwr-led-pin {
    145		marvell,pins = "mpp63";
    146		marvell,function = "gpio";
    147	};
    148
    149	stat_led_pins: stat-led-pins {
    150		marvell,pins = "mpp64", "mpp65";
    151		marvell,function = "gpio";
    152	};
    153};
    154
    155&nand_controller {
    156	status = "okay";
    157
    158	nand@0 {
    159		reg = <0>;
    160		label = "pxa3xx_nand-0";
    161		nand-rb = <0>;
    162		marvell,nand-keep-config;
    163		nand-on-flash-bbt;
    164
    165		partitions {
    166			compatible = "fixed-partitions";
    167			#address-cells = <1>;
    168			#size-cells = <1>;
    169
    170			partition@0 {
    171				label = "U-Boot";
    172				reg = <0 0x400000>;
    173			};
    174			partition@400000 {
    175				label = "Linux";
    176				reg = <0x400000 0x400000>;
    177			};
    178			partition@800000 {
    179				label = "Filesystem";
    180				reg = <0x800000 0x3f800000>;
    181			};
    182		};
    183	};
    184};