cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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armada-370-seagate-personal-cloud.dtsi (3215B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay
      4 * (Armada 370 SoC).
      5 *
      6 * Copyright (C) 2015 Seagate
      7 *
      8 * Author: Simon Guinot <simon.guinot@sequanux.org>
      9 */
     10
     11/*
     12 * TODO: add support for the white SATA LED.
     13 */
     14
     15#include "armada-370.dtsi"
     16#include <dt-bindings/gpio/gpio.h>
     17#include <dt-bindings/input/input.h>
     18
     19/ {
     20	chosen {
     21		stdout-path = "serial0:115200n8";
     22	};
     23
     24	memory@0 {
     25		device_type = "memory";
     26		reg = <0x00000000 0x20000000>; /* 512 MB */
     27	};
     28
     29	soc {
     30		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
     31			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
     32
     33		internal-regs {
     34			coherency-fabric@20200 {
     35				broken-idle;
     36			};
     37
     38			serial@12000 {
     39				status = "okay";
     40			};
     41
     42			ethernet@74000 {
     43				status = "okay";
     44				pinctrl-0 = <&ge1_rgmii_pins>;
     45				pinctrl-names = "default";
     46				phy = <&phy0>;
     47				phy-mode = "rgmii-id";
     48			};
     49
     50			usb@50000 {
     51				status = "okay";
     52			};
     53		};
     54	};
     55
     56	regulators {
     57		compatible = "simple-bus";
     58		#address-cells = <1>;
     59		#size-cells = <0>;
     60
     61		regulator@0 {
     62			compatible = "regulator-fixed";
     63			reg = <0>;
     64			regulator-name = "USB Power";
     65			regulator-min-microvolt = <5000000>;
     66			regulator-max-microvolt = <5000000>;
     67			regulator-always-on;
     68			regulator-boot-on;
     69			gpio = <&gpio1 27 GPIO_ACTIVE_LOW>;
     70		};
     71		regulator@1 {
     72			compatible = "regulator-fixed";
     73			reg = <1>;
     74			regulator-name = "SATA0 power";
     75			regulator-min-microvolt = <5000000>;
     76			regulator-max-microvolt = <5000000>;
     77			enable-active-high;
     78			regulator-always-on;
     79			regulator-boot-on;
     80			gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
     81		};
     82	};
     83
     84	gpio-keys {
     85		compatible = "gpio-keys";
     86		#address-cells = <1>;
     87		#size-cells = <0>;
     88
     89		power {
     90			label = "Power button";
     91			linux,code = <KEY_POWER>;
     92			gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
     93			debounce-interval = <100>;
     94		};
     95		reset {
     96			label = "Reset Button";
     97			linux,code = <KEY_RESTART>;
     98			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
     99			debounce-interval = <100>;
    100		};
    101		button {
    102			label = "USB VBUS error";
    103			linux,code = <KEY_UNKNOWN>;
    104			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
    105			debounce-interval = <100>;
    106		};
    107	};
    108
    109	gpio-leds {
    110		compatible = "gpio-leds";
    111
    112		red-sata0 {
    113			label = "cumulus:red:sata0";
    114			gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
    115			default-state = "off";
    116		};
    117	};
    118
    119	gpio_poweroff {
    120		compatible = "gpio-poweroff";
    121		gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
    122	};
    123};
    124
    125&pciec {
    126	status = "okay";
    127
    128	/* USB 3.0 Bridge ASM1042A */
    129	pcie@1,0 {
    130		status = "okay";
    131	};
    132};
    133
    134&mdio {
    135	pinctrl-0 = <&mdio_pins>;
    136	pinctrl-names = "default";
    137
    138	phy0: ethernet-phy@0 {
    139		reg = <0>;
    140	};
    141};
    142
    143&pinctrl {
    144	pinctrl-0 = <&sata_led_pin>;
    145	pinctrl-names = "default";
    146
    147	sata_led_pin: sata-led-pin {
    148		marvell,pins = "mpp60";
    149		marvell,function = "sata0";
    150	};
    151	gpio_led_pin: gpio-led-pin {
    152		marvell,pins = "mpp60";
    153		marvell,function = "gpio";
    154	};
    155};
    156
    157&spi0 {
    158	status = "okay";
    159	pinctrl-0 = <&spi0_pins2>;
    160	pinctrl-names = "default";
    161
    162	flash@0 {
    163		#address-cells = <1>;
    164		#size-cells = <1>;
    165		/* MX25L8006E */
    166		compatible = "mxicy,mx25l8005", "jedec,spi-nor";
    167		reg = <0>; /* Chip select 0 */
    168		spi-max-frequency = <50000000>;
    169
    170		partition@0 {
    171			label = "u-boot";
    172			reg = <0x0 0x100000>;
    173		};
    174	};
    175};