cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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armada-375-db.dts (2962B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Device Tree file for Marvell Armada 375 evaluation board
      4 * (DB-88F6720)
      5 *
      6 *  Copyright (C) 2014 Marvell
      7 *
      8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
      9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
     10 */
     11
     12/dts-v1/;
     13#include <dt-bindings/gpio/gpio.h>
     14#include "armada-375.dtsi"
     15
     16/ {
     17	model = "Marvell Armada 375 Development Board";
     18	compatible = "marvell,a375-db", "marvell,armada375";
     19
     20	chosen {
     21		stdout-path = "serial0:115200n8";
     22	};
     23
     24	memory@0 {
     25		device_type = "memory";
     26		reg = <0x00000000 0x40000000>; /* 1 GB */
     27	};
     28
     29	soc {
     30		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
     31			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
     32			  MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
     33			  MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
     34
     35	};
     36};
     37&pciec {
     38	status = "okay";
     39};
     40
     41/*
     42 * The two PCIe units are accessible through
     43 * standard PCIe slots on the board.
     44 */
     45&pcie0 {
     46	/* Port 0, Lane 0 */
     47	status = "okay";
     48};
     49
     50&pcie1 {
     51	/* Port 1, Lane 0 */
     52	status = "okay";
     53};
     54
     55
     56&spi0 {
     57	pinctrl-0 = <&spi0_pins>;
     58	pinctrl-names = "default";
     59
     60	/*
     61	 * SPI conflicts with NAND, so we disable it here, and
     62	 * select NAND as the enabled device by default.
     63	 */
     64
     65	status = "disabled";
     66
     67	flash@0 {
     68		#address-cells = <1>;
     69		#size-cells = <1>;
     70		compatible = "n25q128a13", "jedec,spi-nor";
     71		reg = <0>; /* Chip select 0 */
     72		spi-max-frequency = <108000000>;
     73	};
     74};
     75
     76&i2c0 {
     77	status = "okay";
     78	clock-frequency = <100000>;
     79	pinctrl-0 = <&i2c0_pins>;
     80	pinctrl-names = "default";
     81};
     82
     83&i2c1 {
     84	status = "okay";
     85	clock-frequency = <100000>;
     86	pinctrl-0 = <&i2c1_pins>;
     87	pinctrl-names = "default";
     88};
     89
     90&uart0 {
     91	status = "okay";
     92};
     93
     94&pinctrl {
     95	sdio_st_pins: sdio-st-pins {
     96		marvell,pins = "mpp44", "mpp45";
     97		marvell,function = "gpio";
     98	};
     99};
    100
    101&sata {
    102	status = "okay";
    103	nr-ports = <2>;
    104};
    105
    106&nand_controller {
    107	status = "okay";
    108	pinctrl-0 = <&nand_pins>;
    109	pinctrl-names = "default";
    110
    111	nand@0 {
    112		reg = <0>;
    113		label = "pxa3xx_nand-0";
    114		nand-rb = <0>;
    115		marvell,nand-keep-config;
    116		nand-on-flash-bbt;
    117		nand-ecc-strength = <4>;
    118		nand-ecc-step-size = <512>;
    119
    120		partitions {
    121			compatible = "fixed-partitions";
    122			#address-cells = <1>;
    123			#size-cells = <1>;
    124
    125			partition@0 {
    126				label = "U-Boot";
    127				reg = <0 0x800000>;
    128			};
    129			partition@800000 {
    130				label = "Linux";
    131				reg = <0x800000 0x800000>;
    132			};
    133			partition@1000000 {
    134				label = "Filesystem";
    135				reg = <0x1000000 0x3f000000>;
    136			};
    137		};
    138	};
    139};
    140
    141&usb1 {
    142	status = "okay";
    143};
    144
    145&usb2 {
    146	status = "okay";
    147};
    148
    149&sdio {
    150	pinctrl-0 = <&sdio_pins &sdio_st_pins>;
    151	pinctrl-names = "default";
    152	status = "okay";
    153	cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
    154	wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
    155};
    156
    157&mdio {
    158	phy0: ethernet-phy@0 {
    159		reg = <0>;
    160	};
    161
    162	phy3: ethernet-phy@3 {
    163		reg = <3>;
    164	};
    165};
    166
    167&ethernet {
    168	status = "okay";
    169};
    170
    171
    172&eth0 {
    173	status = "okay";
    174	phy = <&phy0>;
    175	phy-mode = "rgmii-id";
    176};
    177
    178&eth1 {
    179	status = "okay";
    180	phy = <&phy3>;
    181	phy-mode = "gmii";
    182};