cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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armada-385-clearfog-gtr-l8.dts (1685B)

      1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
      2
      3#include "armada-385-clearfog-gtr.dtsi"
      4
      5/ {
      6	model = "SolidRun Clearfog GTR L8";
      7};
      8
      9&mdio {
     10	switch0: switch0@4 {
     11		compatible = "marvell,mv88e6190";
     12		reg = <4>;
     13		pinctrl-names = "default";
     14		pinctrl-0 = <&cf_gtr_switch_reset_pins>;
     15		reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
     16
     17		ports {
     18			#address-cells = <1>;
     19			#size-cells = <0>;
     20
     21			port@1 {
     22				reg = <1>;
     23				label = "lan8";
     24				phy-handle = <&switch0phy0>;
     25			};
     26
     27			port@2 {
     28				reg = <2>;
     29				label = "lan7";
     30				phy-handle = <&switch0phy1>;
     31			};
     32
     33			port@3 {
     34				reg = <3>;
     35				label = "lan6";
     36				phy-handle = <&switch0phy2>;
     37			};
     38
     39			port@4 {
     40				reg = <4>;
     41				label = "lan5";
     42				phy-handle = <&switch0phy3>;
     43			};
     44
     45			port@5 {
     46				reg = <5>;
     47				label = "lan4";
     48				phy-handle = <&switch0phy4>;
     49			};
     50
     51			port@6 {
     52				reg = <6>;
     53				label = "lan3";
     54				phy-handle = <&switch0phy5>;
     55			};
     56
     57			port@7 {
     58				reg = <7>;
     59				label = "lan2";
     60				phy-handle = <&switch0phy6>;
     61			};
     62
     63			port@8 {
     64				reg = <8>;
     65				label = "lan1";
     66				phy-handle = <&switch0phy7>;
     67			};
     68
     69			port@10 {
     70				reg = <10>;
     71				label = "cpu";
     72				ethernet = <&eth1>;
     73			};
     74
     75		};
     76
     77		mdio {
     78			#address-cells = <1>;
     79			#size-cells = <0>;
     80
     81			switch0phy0: switch0phy0@1 {
     82				reg = <0x1>;
     83			};
     84
     85			switch0phy1: switch0phy1@2 {
     86				reg = <0x2>;
     87			};
     88
     89			switch0phy2: switch0phy2@3 {
     90				reg = <0x3>;
     91			};
     92
     93			switch0phy3: switch0phy3@4 {
     94				reg = <0x4>;
     95			};
     96
     97			switch0phy4: switch0phy4@5 {
     98				reg = <0x5>;
     99			};
    100
    101			switch0phy5: switch0phy5@6 {
    102				reg = <0x6>;
    103			};
    104
    105			switch0phy6: switch0phy6@7 {
    106				reg = <0x7>;
    107			};
    108
    109			switch0phy7: switch0phy7@8 {
    110				reg = <0x8>;
    111			};
    112		};
    113
    114	};
    115};