cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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armada-385-linksys-rango.dts (3112B)

      1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
      2/*
      3 * Device Tree file for the Linksys WRT3200ACM (Rango)
      4 *
      5 * Copyright (C) 2016 Imre Kaloz <kaloz@openwrt.org>
      6 */
      7
      8/dts-v1/;
      9#include <dt-bindings/gpio/gpio.h>
     10#include <dt-bindings/input/input.h>
     11#include "armada-385-linksys.dtsi"
     12
     13/ {
     14	model = "Linksys WRT3200ACM";
     15	compatible = "linksys,rango", "linksys,armada385", "marvell,armada385",
     16		     "marvell,armada380";
     17};
     18
     19&expander0 {
     20	wan_amber@0 {
     21		label = "rango:amber:wan";
     22		reg = <0x0>;
     23	};
     24
     25	wan_white@1 {
     26		label = "rango:white:wan";
     27		reg = <0x1>;
     28	};
     29
     30	usb2@5 {
     31		label = "rango:white:usb2";
     32		reg = <0x5>;
     33	};
     34
     35	usb3_1@6 {
     36		label = "rango:white:usb3_1";
     37		reg = <0x6>;
     38	};
     39
     40	usb3_2@7 {
     41		label = "rango:white:usb3_2";
     42		reg = <0x7>;
     43	};
     44
     45	wps_white@8 {
     46		label = "rango:white:wps";
     47		reg = <0x8>;
     48	};
     49
     50	wps_amber@9 {
     51		label = "rango:amber:wps";
     52		reg = <0x9>;
     53	};
     54};
     55
     56&gpio_leds {
     57	power {
     58		gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
     59		label = "rango:white:power";
     60	};
     61
     62	sata {
     63		gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
     64		label = "rango:white:sata";
     65	};
     66
     67	wlan_2g {
     68		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
     69		label = "rango:white:wlan_2g";
     70	};
     71
     72	wlan_5g {
     73		gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
     74		label = "rango:white:wlan_5g";
     75	};
     76};
     77
     78&gpio_leds_pins {
     79	marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56";
     80};
     81
     82&nand {
     83	/* AMD/Spansion S34ML02G2 256MiB, OEM Layout */
     84	partitions {
     85		compatible = "fixed-partitions";
     86		#address-cells = <1>;
     87		#size-cells = <1>;
     88
     89		partition@0 {
     90			label = "u-boot";
     91			reg = <0x0000000 0x200000>;  /* 2MiB */
     92			read-only;
     93		};
     94
     95		partition@200000 {
     96			label = "u_env";
     97			reg = <0x200000 0x20000>;    /* 128KiB */
     98		};
     99
    100		partition@220000 {
    101			label = "s_env";
    102			reg = <0x220000 0x40000>;    /* 256KiB */
    103		};
    104
    105		partition@7e0000 {
    106			label = "devinfo";
    107			reg = <0x7e0000 0x40000>;   /* 256KiB */
    108			read-only;
    109		};
    110
    111		partition@820000 {
    112			label = "sysdiag";
    113			reg = <0x820000 0x1e0000>;   /* 1920KiB */
    114			read-only;
    115		};
    116
    117		/* kernel1 overlaps with rootfs1 by design */
    118		partition@a00000 {
    119			label = "kernel1";
    120			reg = <0xa00000 0x5000000>;  /* 80MiB */
    121		};
    122
    123		partition@1000000 {
    124			label = "rootfs1";
    125			reg = <0x1000000 0x4a00000>;  /* 74MiB */
    126		};
    127
    128		/* kernel2 overlaps with rootfs2 by design */
    129		partition@5a00000 {
    130			label = "kernel2";
    131			reg = <0x5a00000 0x5000000>; /* 80MiB */
    132		};
    133
    134		partition@6000000 {
    135			label = "rootfs2";
    136			reg = <0x6000000 0x4a00000>; /* 74MiB */
    137		};
    138
    139		/*
    140		 * 86MiB, last MiB is for the BBT, not writable
    141		 */
    142		partition@aa00000 {
    143			label = "syscfg";
    144			reg = <0xaa00000 0x5600000>;
    145		};
    146
    147		/*
    148		 * Unused area between "s_env" and "devinfo".
    149		 * Moved here because otherwise the renumbered
    150		 * partitions would break the bootloader
    151		 * supplied bootargs
    152		 */
    153		partition@180000 {
    154			label = "unused_area";
    155			reg = <0x260000 0x5c0000>;   /* 5.75MiB */
    156		};
    157	};
    158};
    159
    160&sdhci {
    161	pinctrl-names = "default";
    162	pinctrl-0 = <&sdhci_pins>;
    163	no-1-8-v;
    164	non-removable;
    165	wp-inverted;
    166	bus-width = <8>;
    167	status = "okay";
    168};
    169
    170&usb3_1_vbus {
    171	gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
    172};
    173
    174&usb3_1_vbus_pins {
    175	marvell,pins = "mpp44";
    176};