cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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armada-385-linksys.dtsi (4364B)


      1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
      2/*
      3 * Device Tree include file for Armada 385 based Linksys boards
      4 *
      5 * Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
      6 */
      7
      8#include <dt-bindings/gpio/gpio.h>
      9#include <dt-bindings/input/input.h>
     10#include "armada-385.dtsi"
     11
     12/ {
     13	model = "Linksys boards based on Armada 385";
     14	compatible = "linksys,armada385", "marvell,armada385",
     15		     "marvell,armada380";
     16
     17	chosen {
     18		stdout-path = "serial0:115200n8";
     19	};
     20
     21	memory {
     22		device_type = "memory";
     23		reg = <0x00000000 0x20000000>; /* 512 MiB */
     24	};
     25
     26	soc {
     27		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
     28			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
     29			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
     30			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
     31			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
     32	};
     33
     34	usb3_1_phy: usb3_1-phy {
     35		compatible = "usb-nop-xceiv";
     36		vcc-supply = <&usb3_1_vbus>;
     37		#phy-cells = <0>;
     38	};
     39
     40	usb3_1_vbus: usb3_1-vbus {
     41		compatible = "regulator-fixed";
     42		pinctrl-names = "default";
     43		pinctrl-0 = <&usb3_1_vbus_pins>;
     44		regulator-name = "usb3_1-vbus";
     45		regulator-min-microvolt = <5000000>;
     46		regulator-max-microvolt = <5000000>;
     47		enable-active-high;
     48		gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
     49	};
     50
     51	gpio_keys: gpio-keys {
     52		compatible = "gpio-keys";
     53		pinctrl-0 = <&gpio_keys_pins>;
     54		pinctrl-names = "default";
     55
     56		wps {
     57			label = "WPS";
     58			linux,code = <KEY_WPS_BUTTON>;
     59			gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
     60		};
     61
     62		reset {
     63			label = "Factory Reset Button";
     64			linux,code = <KEY_RESTART>;
     65			gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
     66		};
     67	};
     68
     69	gpio_leds: gpio-leds {
     70		compatible = "gpio-leds";
     71		pinctrl-0 = <&gpio_leds_pins>;
     72		pinctrl-names = "default";
     73
     74		power {
     75			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
     76			default-state = "on";
     77		};
     78
     79		sata {
     80			gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
     81			default-state = "off";
     82			linux,default-trigger = "disk-activity";
     83		};
     84	};
     85};
     86
     87&ahci0 {
     88	status = "okay";
     89};
     90
     91&bm {
     92	status = "okay";
     93};
     94
     95&bm_bppi {
     96	status = "okay";
     97};
     98
     99&eth0 {
    100	status = "okay";
    101	phy-mode = "rgmii-id";
    102	buffer-manager = <&bm>;
    103	bm,pool-long = <0>;
    104	bm,pool-short = <1>;
    105	fixed-link {
    106		speed = <1000>;
    107		full-duplex;
    108	};
    109};
    110
    111&eth2 {
    112	status = "okay";
    113	phy-mode = "sgmii";
    114	buffer-manager = <&bm>;
    115	bm,pool-long = <2>;
    116	bm,pool-short = <3>;
    117	fixed-link {
    118		speed = <1000>;
    119		full-duplex;
    120	};
    121};
    122
    123&i2c0 {
    124	pinctrl-names = "default";
    125	pinctrl-0 = <&i2c0_pins>;
    126	status = "okay";
    127
    128	tmp421@4c {
    129		compatible = "ti,tmp421";
    130		reg = <0x4c>;
    131	};
    132
    133	expander0: pca9635@68 {
    134		#address-cells = <1>;
    135		#size-cells = <0>;
    136		compatible = "nxp,pca9635";
    137		reg = <0x68>;
    138	};
    139};
    140
    141&nand_controller {
    142	/* 128MiB or 256MiB */
    143	status = "okay";
    144	#address-cells = <1>;
    145	#size-cells = <0>;
    146
    147	nand: nand@0 {
    148		reg = <0>;
    149		label = "pxa3xx_nand-0";
    150		nand-rb = <0>;
    151		nand-ecc-strength = <4>;
    152		nand-ecc-step-size = <512>;
    153		marvell,nand-keep-config;
    154		nand-on-flash-bbt;
    155	};
    156};
    157
    158&mdio {
    159	status = "okay";
    160
    161	switch@0 {
    162		compatible = "marvell,mv88e6085";
    163		#address-cells = <1>;
    164		#size-cells = <0>;
    165		reg = <0>;
    166
    167		ports {
    168			#address-cells = <1>;
    169			#size-cells = <0>;
    170
    171			port@0 {
    172				reg = <0>;
    173				label = "lan4";
    174			};
    175
    176			port@1 {
    177				reg = <1>;
    178				label = "lan3";
    179			};
    180
    181			port@2 {
    182				reg = <2>;
    183				label = "lan2";
    184			};
    185
    186			port@3 {
    187				reg = <3>;
    188				label = "lan1";
    189			};
    190
    191			port@4 {
    192				reg = <4>;
    193				label = "wan";
    194			};
    195
    196			port@5 {
    197				reg = <5>;
    198				label = "cpu";
    199				ethernet = <&eth2>;
    200
    201				fixed-link {
    202					speed = <1000>;
    203					full-duplex;
    204				};
    205			};
    206		};
    207	};
    208};
    209
    210&pciec {
    211	status = "okay";
    212};
    213
    214&pcie1 {
    215	/* Marvell 88W8864, 5GHz-only */
    216	status = "okay";
    217};
    218
    219&pcie2 {
    220	/* Marvell 88W8864, 2GHz-only */
    221	status = "okay";
    222};
    223
    224&pinctrl {
    225	gpio_keys_pins: gpio-keys-pins {
    226		/* mpp24: wps, mpp29: reset */
    227		marvell,pins = "mpp24", "mpp29";
    228		marvell,function = "gpio";
    229	};
    230
    231	gpio_leds_pins: gpio-leds-pins {
    232		/* mpp54: sata, mpp55: power */
    233		marvell,pins = "mpp54", "mpp55";
    234		marvell,function = "gpio";
    235	};
    236
    237	usb3_1_vbus_pins: usb3_1-vbus-pins {
    238		marvell,pins = "mpp50";
    239		marvell,function = "gpio";
    240	};
    241};
    242
    243&spi0 {
    244	status = "disabled";
    245};
    246
    247&uart0 {
    248	/* J10: VCC, NC, RX, NC, TX, GND  */
    249	status = "okay";
    250};
    251
    252&usb0 {
    253	/* USB part of the eSATA/USB 2.0 port */
    254	status = "okay";
    255};
    256
    257&usb3_1 {
    258	status = "okay";
    259	usb-phy = <&usb3_1_phy>;
    260};
    261
    262&rtc {
    263	/* No crystal connected to the internal RTC */
    264	status = "disabled";
    265};