armada-388-gp.dts (8845B)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Device Tree file for Marvell Armada 385 development board 4 * (RD-88F6820-GP) 5 * 6 * Copyright (C) 2014 Marvell 7 * 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 9 */ 10 11/dts-v1/; 12#include "armada-388.dtsi" 13#include <dt-bindings/gpio/gpio.h> 14 15/ { 16 model = "Marvell Armada 388 DB-88F6820-GP"; 17 compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380"; 18 19 chosen { 20 stdout-path = "serial0:115200n8"; 21 }; 22 23 memory { 24 device_type = "memory"; 25 reg = <0x00000000 0x80000000>; /* 2 GB */ 26 }; 27 28 soc { 29 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 30 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 31 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 32 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000 33 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; 34 35 internal-regs { 36 i2c@11000 { 37 pinctrl-names = "default"; 38 pinctrl-0 = <&i2c0_pins>; 39 status = "okay"; 40 clock-frequency = <100000>; 41 42 expander0: pca9555@20 { 43 compatible = "nxp,pca9555"; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pca0_pins>; 46 interrupt-parent = <&gpio0>; 47 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 48 gpio-controller; 49 #gpio-cells = <2>; 50 interrupt-controller; 51 #interrupt-cells = <2>; 52 reg = <0x20>; 53 }; 54 55 expander1: pca9555@21 { 56 compatible = "nxp,pca9555"; 57 pinctrl-names = "default"; 58 interrupt-parent = <&gpio0>; 59 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 60 gpio-controller; 61 #gpio-cells = <2>; 62 interrupt-controller; 63 #interrupt-cells = <2>; 64 reg = <0x21>; 65 }; 66 67 eeprom@57 { 68 compatible = "atmel,24c64"; 69 reg = <0x57>; 70 }; 71 }; 72 73 serial@12000 { 74 /* 75 * Exported on the micro USB connector CON16 76 * through an FTDI 77 */ 78 79 pinctrl-names = "default"; 80 pinctrl-0 = <&uart0_pins>; 81 status = "okay"; 82 }; 83 84 /* GE1 CON15 */ 85 ethernet@30000 { 86 pinctrl-names = "default"; 87 pinctrl-0 = <&ge1_rgmii_pins>; 88 status = "okay"; 89 phy = <&phy1>; 90 phy-mode = "rgmii-id"; 91 buffer-manager = <&bm>; 92 bm,pool-long = <2>; 93 bm,pool-short = <3>; 94 }; 95 96 /* CON4 */ 97 usb@58000 { 98 vcc-supply = <®_usb2_0_vbus>; 99 status = "okay"; 100 }; 101 102 /* GE0 CON1 */ 103 ethernet@70000 { 104 pinctrl-names = "default"; 105 /* 106 * The Reference Clock 0 is used to provide a 107 * clock to the PHY 108 */ 109 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; 110 status = "okay"; 111 phy = <&phy0>; 112 phy-mode = "rgmii-id"; 113 buffer-manager = <&bm>; 114 bm,pool-long = <0>; 115 bm,pool-short = <1>; 116 }; 117 118 119 mdio@72004 { 120 pinctrl-names = "default"; 121 pinctrl-0 = <&mdio_pins>; 122 123 phy0: ethernet-phy@1 { 124 reg = <1>; 125 }; 126 127 phy1: ethernet-phy@0 { 128 reg = <0>; 129 }; 130 }; 131 132 sata@a8000 { 133 pinctrl-names = "default"; 134 pinctrl-0 = <&sata0_pins>, <&sata1_pins>; 135 status = "okay"; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 sata0: sata-port@0 { 140 reg = <0>; 141 target-supply = <®_5v_sata0>; 142 }; 143 144 sata1: sata-port@1 { 145 reg = <1>; 146 target-supply = <®_5v_sata1>; 147 }; 148 }; 149 150 bm@c8000 { 151 status = "okay"; 152 }; 153 154 sata@e0000 { 155 pinctrl-names = "default"; 156 pinctrl-0 = <&sata2_pins>, <&sata3_pins>; 157 status = "okay"; 158 #address-cells = <1>; 159 #size-cells = <0>; 160 161 sata2: sata-port@0 { 162 reg = <0>; 163 target-supply = <®_5v_sata2>; 164 }; 165 166 sata3: sata-port@1 { 167 reg = <1>; 168 target-supply = <®_5v_sata3>; 169 }; 170 }; 171 172 sdhci@d8000 { 173 pinctrl-names = "default"; 174 pinctrl-0 = <&sdhci_pins>; 175 no-1-8-v; 176 /* 177 * A388-GP board v1.5 and higher replace 178 * hitherto card detection method based on GPIO 179 * with the one using DAT3 pin. As they are 180 * incompatible, software-based polling is 181 * enabled with 'broken-cd' property. For boards 182 * older than v1.5 it can be replaced with: 183 * 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;', 184 * whereas for the newer ones following can be 185 * used instead: 186 * 'dat3-cd;' 187 * 'cd-inverted;' 188 */ 189 broken-cd; 190 wp-inverted; 191 bus-width = <8>; 192 status = "okay"; 193 }; 194 195 /* CON5 */ 196 usb3@f0000 { 197 usb-phy = <&usb2_1_phy>; 198 status = "okay"; 199 }; 200 201 /* CON7 */ 202 usb3@f8000 { 203 usb-phy = <&usb3_phy>; 204 status = "okay"; 205 }; 206 }; 207 208 bm-bppi { 209 status = "okay"; 210 }; 211 212 pcie { 213 status = "okay"; 214 /* 215 * One PCIe units is accessible through 216 * standard PCIe slot on the board. 217 */ 218 pcie@1,0 { 219 /* Port 0, Lane 0 */ 220 status = "okay"; 221 }; 222 223 /* 224 * The two other PCIe units are accessible 225 * through mini PCIe slot on the board. 226 */ 227 pcie@2,0 { 228 /* Port 1, Lane 0 */ 229 status = "okay"; 230 }; 231 pcie@3,0 { 232 /* Port 2, Lane 0 */ 233 status = "okay"; 234 }; 235 }; 236 237 gpio-fan { 238 compatible = "gpio-fan"; 239 gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; 240 gpio-fan,speed-map = < 0 0 241 3000 1>; 242 }; 243 }; 244 245 usb2_1_phy: usb2_1_phy { 246 compatible = "usb-nop-xceiv"; 247 vcc-supply = <®_usb2_1_vbus>; 248 #phy-cells = <0>; 249 }; 250 251 usb3_phy: usb3_phy { 252 compatible = "usb-nop-xceiv"; 253 vcc-supply = <®_usb3_vbus>; 254 #phy-cells = <0>; 255 }; 256 257 reg_usb3_vbus: usb3-vbus { 258 compatible = "regulator-fixed"; 259 regulator-name = "usb3-vbus"; 260 regulator-min-microvolt = <5000000>; 261 regulator-max-microvolt = <5000000>; 262 enable-active-high; 263 gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; 264 }; 265 266 reg_usb2_0_vbus: v5-vbus0 { 267 compatible = "regulator-fixed"; 268 regulator-name = "v5.0-vbus0"; 269 regulator-min-microvolt = <5000000>; 270 regulator-max-microvolt = <5000000>; 271 enable-active-high; 272 regulator-always-on; 273 gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; 274 }; 275 276 reg_usb2_1_vbus: v5-vbus1 { 277 compatible = "regulator-fixed"; 278 regulator-name = "v5.0-vbus1"; 279 regulator-min-microvolt = <5000000>; 280 regulator-max-microvolt = <5000000>; 281 enable-active-high; 282 gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; 283 }; 284 285 reg_sata0: pwr-sata0 { 286 compatible = "regulator-fixed"; 287 regulator-name = "pwr_en_sata0"; 288 regulator-min-microvolt = <12000000>; 289 regulator-max-microvolt = <12000000>; 290 enable-active-high; 291 regulator-boot-on; 292 gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; 293 }; 294 295 reg_5v_sata0: v5-sata0 { 296 compatible = "regulator-fixed"; 297 regulator-name = "v5.0-sata0"; 298 regulator-min-microvolt = <5000000>; 299 regulator-max-microvolt = <5000000>; 300 vin-supply = <®_sata0>; 301 }; 302 303 reg_12v_sata0: v12-sata0 { 304 compatible = "regulator-fixed"; 305 regulator-name = "v12.0-sata0"; 306 regulator-min-microvolt = <12000000>; 307 regulator-max-microvolt = <12000000>; 308 vin-supply = <®_sata0>; 309 }; 310 311 reg_sata1: pwr-sata1 { 312 regulator-name = "pwr_en_sata1"; 313 compatible = "regulator-fixed"; 314 regulator-min-microvolt = <12000000>; 315 regulator-max-microvolt = <12000000>; 316 enable-active-high; 317 regulator-boot-on; 318 gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; 319 }; 320 321 reg_5v_sata1: v5-sata1 { 322 compatible = "regulator-fixed"; 323 regulator-name = "v5.0-sata1"; 324 regulator-min-microvolt = <5000000>; 325 regulator-max-microvolt = <5000000>; 326 vin-supply = <®_sata1>; 327 }; 328 329 reg_12v_sata1: v12-sata1 { 330 compatible = "regulator-fixed"; 331 regulator-name = "v12.0-sata1"; 332 regulator-min-microvolt = <12000000>; 333 regulator-max-microvolt = <12000000>; 334 vin-supply = <®_sata1>; 335 }; 336 337 reg_sata2: pwr-sata2 { 338 compatible = "regulator-fixed"; 339 regulator-name = "pwr_en_sata2"; 340 enable-active-high; 341 regulator-boot-on; 342 gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; 343 }; 344 345 reg_5v_sata2: v5-sata2 { 346 compatible = "regulator-fixed"; 347 regulator-name = "v5.0-sata2"; 348 regulator-min-microvolt = <5000000>; 349 regulator-max-microvolt = <5000000>; 350 vin-supply = <®_sata2>; 351 }; 352 353 reg_12v_sata2: v12-sata2 { 354 compatible = "regulator-fixed"; 355 regulator-name = "v12.0-sata2"; 356 regulator-min-microvolt = <12000000>; 357 regulator-max-microvolt = <12000000>; 358 vin-supply = <®_sata2>; 359 }; 360 361 reg_sata3: pwr-sata3 { 362 compatible = "regulator-fixed"; 363 regulator-name = "pwr_en_sata3"; 364 enable-active-high; 365 regulator-boot-on; 366 gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; 367 }; 368 369 reg_5v_sata3: v5-sata3 { 370 compatible = "regulator-fixed"; 371 regulator-name = "v5.0-sata3"; 372 regulator-min-microvolt = <5000000>; 373 regulator-max-microvolt = <5000000>; 374 vin-supply = <®_sata3>; 375 }; 376 377 reg_12v_sata3: v12-sata3 { 378 compatible = "regulator-fixed"; 379 regulator-name = "v12.0-sata3"; 380 regulator-min-microvolt = <12000000>; 381 regulator-max-microvolt = <12000000>; 382 vin-supply = <®_sata3>; 383 }; 384}; 385 386&pinctrl { 387 pca0_pins: pca0_pins { 388 marvell,pins = "mpp18"; 389 marvell,function = "gpio"; 390 }; 391}; 392 393&spi0 { 394 pinctrl-names = "default"; 395 pinctrl-0 = <&spi0_pins>; 396 status = "okay"; 397 398 flash@0 { 399 #address-cells = <1>; 400 #size-cells = <1>; 401 compatible = "st,m25p128", "jedec,spi-nor"; 402 reg = <0>; /* Chip select 0 */ 403 spi-max-frequency = <50000000>; 404 m25p,fast-read; 405 }; 406};