cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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armada-398-db.dts (2266B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Device Tree Include file for Marvell Armada 398 Development Board
      4 *
      5 * Copyright (C) 2015 Marvell
      6 *
      7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
      8 */
      9
     10/dts-v1/;
     11#include "armada-398.dtsi"
     12
     13/ {
     14	model = "Marvell Armada 398 Development Board";
     15	compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
     16
     17	chosen {
     18		stdout-path = "serial0:115200n8";
     19	};
     20
     21	memory {
     22		device_type = "memory";
     23		reg = <0x00000000 0x80000000>; /* 2 GB */
     24	};
     25
     26	soc {
     27		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
     28			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
     29
     30		internal-regs {
     31			i2c@11000 {
     32				pinctrl-0 = <&i2c0_pins>;
     33				pinctrl-names = "default";
     34				status = "okay";
     35				clock-frequency = <100000>;
     36			};
     37
     38			serial@12000 {
     39				pinctrl-0 = <&uart0_pins>;
     40				pinctrl-names = "default";
     41				status = "okay";
     42			};
     43
     44			serial@12100 {
     45				pinctrl-0 = <&uart1_pins>;
     46				pinctrl-names = "default";
     47				status = "okay";
     48			};
     49
     50			usb@58000 {
     51				status = "okay";
     52			};
     53
     54			usb3@f8000 {
     55				status = "okay";
     56			};
     57		};
     58
     59		pcie {
     60			status = "okay";
     61
     62			pcie@1,0 {
     63				status = "okay";
     64			};
     65
     66			pcie@2,0 {
     67				status = "okay";
     68			};
     69
     70			pcie@3,0 {
     71				status = "okay";
     72			};
     73		};
     74	};
     75};
     76
     77&spi1 {
     78	status = "okay";
     79	pinctrl-0 = <&spi1_pins>;
     80	pinctrl-names = "default";
     81
     82	flash@0 {
     83		#address-cells = <1>;
     84		#size-cells = <0>;
     85		compatible = "n25q128a13", "jedec,spi-nor";
     86		reg = <0>;
     87		spi-max-frequency = <108000000>;
     88
     89		partition@0 {
     90			label = "U-Boot";
     91			reg = <0 0x400000>;
     92		};
     93
     94		partition@400000 {
     95			label = "Filesystem";
     96			reg = <0x400000 0x1000000>;
     97		};
     98	};
     99};
    100
    101&nand_controller {
    102	status = "okay";
    103	pinctrl-0 = <&nand_pins>;
    104	pinctrl-names = "default";
    105
    106	nand@0 {
    107		reg = <0>;
    108		label = "pxa3xx_nand-0";
    109		nand-rb = <0>;
    110		marvell,nand-keep-config;
    111		nand-on-flash-bbt;
    112		nand-ecc-strength = <8>;
    113		nand-ecc-step-size = <512>;
    114
    115		partitions {
    116			compatible = "fixed-partitions";
    117			#address-cells = <1>;
    118			#size-cells = <1>;
    119
    120			partition@0 {
    121				label = "U-Boot";
    122				reg = <0 0x800000>;
    123			};
    124			partition@800000 {
    125				label = "Linux";
    126				reg = <0x800000 0x800000>;
    127			};
    128			partition@1000000 {
    129				label = "Filesystem";
    130				reg = <0x1000000 0x3f000000>;
    131			};
    132		};
    133	};
    134};