cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

armada-xp-db-dxbc2.dts (2420B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Device Tree file for DB-DXBC2 board
      4 *
      5 * Copyright (C) 2016 Allied Telesis Labs
      6 *
      7 * Based on armada-xp-db.dts
      8 *
      9 * Note: this Device Tree assumes that the bootloader has remapped the
     10 * internal registers to 0xf1000000 (instead of the default
     11 * 0xd0000000). The 0xf1000000 is the default used by the recent,
     12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
     13 * boards were delivered with an older version of the bootloader that
     14 * left internal registers mapped at 0xd0000000. If you are in this
     15 * situation, you should either update your bootloader (preferred
     16 * solution) or the below Device Tree should be adjusted.
     17 */
     18
     19/dts-v1/;
     20#include "armada-xp-98dx4251.dtsi"
     21
     22/ {
     23	model = "Marvell Bobcat2 Evaluation Board";
     24	compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
     25
     26	chosen {
     27		bootargs = "console=ttyS0,115200 earlyprintk";
     28	};
     29
     30	memory {
     31		device_type = "memory";
     32		reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
     33	};
     34
     35};
     36
     37&devbus_bootcs {
     38	status = "okay";
     39
     40	/* Device Bus parameters are required */
     41
     42	/* Read parameters */
     43	devbus,bus-width    = <16>;
     44	devbus,turn-off-ps  = <60000>;
     45	devbus,badr-skew-ps = <0>;
     46	devbus,acc-first-ps = <124000>;
     47	devbus,acc-next-ps  = <248000>;
     48	devbus,rd-setup-ps  = <0>;
     49	devbus,rd-hold-ps   = <0>;
     50
     51	/* Write parameters */
     52	devbus,sync-enable = <0>;
     53	devbus,wr-high-ps  = <60000>;
     54	devbus,wr-low-ps   = <60000>;
     55	devbus,ale-wr-ps   = <60000>;
     56};
     57
     58&i2c0 {
     59	clock-frequency = <100000>;
     60	status = "okay";
     61};
     62
     63&uart0 {
     64	status = "okay";
     65};
     66
     67&uart1 {
     68	status = "okay";
     69};
     70
     71&nand_controller {
     72	status = "okay";
     73
     74	nand@0 {
     75		reg = <0>;
     76		label = "pxa3xx_nand-0";
     77		nand-rb = <0>;
     78		marvell,nand-keep-config;
     79		nand-on-flash-bbt;
     80		nand-ecc-strength = <4>;
     81		nand-ecc-step-size = <512>;
     82	};
     83};
     84
     85&sdio {
     86	pinctrl-0 = <&sdio_pins>;
     87	pinctrl-names = "default";
     88	status = "okay";
     89	/* No CD or WP GPIOs */
     90	broken-cd;
     91};
     92
     93&spi0 {
     94	status = "okay";
     95
     96	flash@0 {
     97		#address-cells = <1>;
     98		#size-cells = <1>;
     99		compatible = "m25p64";
    100		reg = <0>; /* Chip select 0 */
    101		spi-max-frequency = <20000000>;
    102		m25p,fast-read;
    103
    104		partition@u-boot {
    105			reg = <0x00000000 0x00100000>;
    106			label = "u-boot";
    107		};
    108		partition@u-boot-env {
    109			reg = <0x00100000 0x00040000>;
    110			label = "u-boot-env";
    111		};
    112		partition@unused {
    113			reg = <0x00140000 0x00ec0000>;
    114			label = "unused";
    115		};
    116
    117	};
    118};