cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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armada-xp-db-xc3-24g4xg.dts (2337B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Device Tree file for DB-XC3-24G4XG board
      4 *
      5 * Copyright (C) 2016 Allied Telesis Labs
      6 *
      7 * Based on armada-xp-db.dts
      8 *
      9 * Note: this Device Tree assumes that the bootloader has remapped the
     10 * internal registers to 0xf1000000 (instead of the default
     11 * 0xd0000000). The 0xf1000000 is the default used by the recent,
     12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
     13 * boards were delivered with an older version of the bootloader that
     14 * left internal registers mapped at 0xd0000000. If you are in this
     15 * situation, you should either update your bootloader (preferred
     16 * solution) or the below Device Tree should be adjusted.
     17 */
     18
     19/dts-v1/;
     20#include "armada-xp-98dx3336.dtsi"
     21
     22/ {
     23	model = "DB-XC3-24G4XG";
     24	compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";
     25
     26	chosen {
     27		bootargs = "console=ttyS0,115200 earlyprintk";
     28	};
     29
     30	memory {
     31		device_type = "memory";
     32		reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
     33	};
     34};
     35
     36&L2 {
     37	arm,parity-enable;
     38	marvell,ecc-enable;
     39};
     40
     41&devbus_bootcs {
     42	status = "okay";
     43
     44	/* Device Bus parameters are required */
     45
     46	/* Read parameters */
     47	devbus,bus-width    = <16>;
     48	devbus,turn-off-ps  = <60000>;
     49	devbus,badr-skew-ps = <0>;
     50	devbus,acc-first-ps = <124000>;
     51	devbus,acc-next-ps  = <248000>;
     52	devbus,rd-setup-ps  = <0>;
     53	devbus,rd-hold-ps   = <0>;
     54
     55	/* Write parameters */
     56	devbus,sync-enable = <0>;
     57	devbus,wr-high-ps  = <60000>;
     58	devbus,wr-low-ps   = <60000>;
     59	devbus,ale-wr-ps   = <60000>;
     60};
     61
     62&uart0 {
     63	status = "okay";
     64};
     65
     66&uart1 {
     67	status = "okay";
     68};
     69
     70&i2c0 {
     71	clock-frequency = <100000>;
     72	status = "okay";
     73};
     74
     75&nand_controller {
     76	status = "okay";
     77
     78	nand@0 {
     79		reg = <0>;
     80		label = "pxa3xx_nand-0";
     81		nand-rb = <0>;
     82		marvell,nand-keep-config;
     83		nand-on-flash-bbt;
     84		nand-ecc-strength = <4>;
     85		nand-ecc-step-size = <512>;
     86	};
     87};
     88
     89&spi0 {
     90	status = "okay";
     91
     92	flash@0 {
     93		#address-cells = <1>;
     94		#size-cells = <1>;
     95		compatible = "m25p64";
     96		reg = <0>; /* Chip select 0 */
     97		spi-max-frequency = <20000000>;
     98		m25p,fast-read;
     99
    100		partition@u-boot {
    101			reg = <0x00000000 0x00100000>;
    102			label = "u-boot";
    103		};
    104		partition@u-boot-env {
    105			reg = <0x00100000 0x00040000>;
    106			label = "u-boot-env";
    107		};
    108		partition@unused {
    109			reg = <0x00140000 0x00ec0000>;
    110			label = "unused";
    111		};
    112
    113	};
    114};