cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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armada-xp-matrix.dts (1417B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Device Tree file for Marvell Armada XP Matrix board
      4 *
      5 * Copyright (C) 2013 Marvell
      6 *
      7 * Lior Amsalem <alior@marvell.com>
      8 */
      9
     10/dts-v1/;
     11#include "armada-xp-mv78460.dtsi"
     12
     13/ {
     14	model = "Marvell Armada XP Matrix Board";
     15	compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
     16
     17	chosen {
     18		stdout-path = "serial0:115200n8";
     19	};
     20
     21	memory@0 {
     22		device_type = "memory";
     23		/*
     24		 * This board has 4 GB of RAM, but the last 256 MB of
     25		 * RAM are not usable due to the overlap with the MBus
     26		 * Window address range
     27		 */
     28		reg = <0 0x00000000 0 0xf0000000>;
     29	};
     30
     31	soc {
     32		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
     33			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
     34			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
     35			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
     36
     37		internal-regs {
     38			serial@12000 {
     39				status = "okay";
     40			};
     41			serial@12100 {
     42				status = "okay";
     43			};
     44			serial@12200 {
     45				status = "okay";
     46			};
     47			serial@12300 {
     48				status = "okay";
     49			};
     50
     51			sata@a0000 {
     52				nr-ports = <2>;
     53				status = "okay";
     54			};
     55
     56			ethernet@30000 {
     57				status = "okay";
     58				phy-mode = "sgmii";
     59				fixed-link {
     60					speed = <1000>;
     61					full-duplex;
     62				};
     63			};
     64
     65			usb@50000 {
     66				status = "okay";
     67			};
     68		};
     69	};
     70};
     71
     72&pciec {
     73	status = "okay";
     74
     75	pcie@1,0 {
     76		/* Port 0, Lane 0 */
     77		status = "okay";
     78	};
     79};