cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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armada-xp-synology-ds414.dts (7688B)


      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Device Tree file for Synology DS414
      4 *
      5 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
      6 *
      7 * Note: this Device Tree assumes that the bootloader has remapped the
      8 * internal registers to 0xf1000000 (instead of the old 0xd0000000).
      9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
     10 * bootloaders provided by Marvell. It is used in recent versions of
     11 * DSM software provided by Synology. Nonetheless, some earlier boards
     12 * were delivered with an older version of u-boot that left internal
     13 * registers mapped at 0xd0000000. If you have such a device you will
     14 * not be able to directly boot a kernel based on this Device Tree. In
     15 * that case, the preferred solution is to update your bootloader (e.g.
     16 * by upgrading to latest version of DSM, or building a new one and
     17 * installing it from u-boot prompt) or adjust the Devive Tree
     18 * (s/0xf1000000/0xd0000000/ in 'ranges' below).
     19 */
     20
     21/dts-v1/;
     22
     23#include <dt-bindings/input/input.h>
     24#include <dt-bindings/gpio/gpio.h>
     25#include "armada-xp-mv78230.dtsi"
     26
     27/ {
     28	model = "Synology DS414";
     29	compatible = "synology,ds414", "marvell,armadaxp-mv78230",
     30		     "marvell,armadaxp", "marvell,armada-370-xp";
     31
     32	chosen {
     33		stdout-path = "serial0:115200n8";
     34	};
     35
     36	memory@0 {
     37		device_type = "memory";
     38		reg = <0 0x00000000 0 0x40000000>; /* 1GB */
     39	};
     40
     41	soc {
     42		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
     43			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
     44			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
     45			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
     46
     47		internal-regs {
     48
     49			/* RTC is provided by Seiko S-35390A below */
     50			rtc@10300 {
     51				status = "disabled";
     52			};
     53
     54			i2c@11000 {
     55				clock-frequency = <400000>;
     56				status = "okay";
     57
     58				s35390a: s35390a@30 {
     59					 compatible = "sii,s35390a";
     60					 reg = <0x30>;
     61				};
     62			};
     63
     64			/* Connected to a header on device's PCB. This
     65			 * provides the main console for the device.
     66			 *
     67			 * Warning: the device may not boot with a 3.3V
     68			 * USB-serial converter connected when the power
     69			 * button is pressed. The converter needs to be
     70			 * connected a few seconds after pressing the
     71			 * power button. This is possibly due to UART0_TXD
     72			 * pin being sampled at reset (bit 0 of SAR).
     73			 */
     74			serial@12000 {
     75				status = "okay";
     76			};
     77
     78			/* Connected to a Microchip PIC16F883 for power control */
     79			serial@12100 {
     80				status = "okay";
     81			};
     82
     83			poweroff@12100 {
     84				compatible = "synology,power-off";
     85				reg = <0x12100 0x100>;
     86				clocks = <&coreclk 0>;
     87			};
     88
     89			/* Front USB 2.0 port */
     90			usb@50000 {
     91				status = "okay";
     92			};
     93
     94			ethernet@70000 {
     95				status = "okay";
     96				pinctrl-0 = <&ge0_rgmii_pins>;
     97				pinctrl-names = "default";
     98				phy = <&phy1>;
     99				phy-mode = "rgmii-id";
    100			};
    101
    102			ethernet@74000 {
    103				pinctrl-0 = <&ge1_rgmii_pins>;
    104				pinctrl-names = "default";
    105				status = "okay";
    106				phy = <&phy0>;
    107				phy-mode = "rgmii-id";
    108			};
    109		};
    110	};
    111
    112	regulators {
    113		compatible = "simple-bus";
    114		#address-cells = <1>;
    115		#size-cells = <0>;
    116		pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin
    117			     &sata3_pwr_pin &sata4_pwr_pin>;
    118		pinctrl-names = "default";
    119
    120		sata1_regulator: sata1-regulator@1 {
    121			compatible = "regulator-fixed";
    122			reg = <1>;
    123			regulator-name = "SATA1 Power";
    124			regulator-min-microvolt = <5000000>;
    125			regulator-max-microvolt = <5000000>;
    126			startup-delay-us = <2000000>;
    127			enable-active-high;
    128			regulator-always-on;
    129			regulator-boot-on;
    130			gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
    131		};
    132
    133		sata2_regulator: sata2-regulator@2 {
    134			compatible = "regulator-fixed";
    135			reg = <2>;
    136			regulator-name = "SATA2 Power";
    137			regulator-min-microvolt = <5000000>;
    138			regulator-max-microvolt = <5000000>;
    139			startup-delay-us = <4000000>;
    140			enable-active-high;
    141			regulator-always-on;
    142			regulator-boot-on;
    143			gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
    144		};
    145
    146		sata3_regulator: sata3-regulator@3 {
    147			compatible = "regulator-fixed";
    148			reg = <3>;
    149			regulator-name = "SATA3 Power";
    150			regulator-min-microvolt = <5000000>;
    151			regulator-max-microvolt = <5000000>;
    152			startup-delay-us = <6000000>;
    153			enable-active-high;
    154			regulator-always-on;
    155			regulator-boot-on;
    156			gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
    157		};
    158
    159		sata4_regulator: sata4-regulator@4 {
    160			compatible = "regulator-fixed";
    161			reg = <4>;
    162			regulator-name = "SATA4 Power";
    163			regulator-min-microvolt = <5000000>;
    164			regulator-max-microvolt = <5000000>;
    165			startup-delay-us = <8000000>;
    166			enable-active-high;
    167			regulator-always-on;
    168			regulator-boot-on;
    169			gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
    170		};
    171	};
    172};
    173
    174&pciec {
    175	status = "okay";
    176
    177	/*
    178	 * Connected to Marvell 88SX7042 SATA-II controller
    179	 * handling the four disks.
    180	 */
    181	pcie@1,0 {
    182		/* Port 0, Lane 0 */
    183		status = "okay";
    184	};
    185
    186	/*
    187	 * Connected to EtronTech EJ168A XHCI controller
    188	 * providing the two rear USB 3.0 ports.
    189	 */
    190	pcie@5,0 {
    191		/* Port 1, Lane 0 */
    192		status = "okay";
    193	};
    194};
    195
    196
    197&mdio {
    198	phy0: ethernet-phy@0 { /* Marvell 88E1512 */
    199		reg = <0>;
    200	};
    201
    202	phy1: ethernet-phy@1 { /* Marvell 88E1512 */
    203		reg = <1>;
    204	};
    205};
    206
    207&pinctrl {
    208	sata1_pwr_pin: sata1-pwr-pin {
    209		marvell,pins = "mpp42";
    210		marvell,function = "gpio";
    211	};
    212
    213	sata2_pwr_pin: sata2-pwr-pin {
    214		marvell,pins = "mpp44";
    215		marvell,function = "gpio";
    216	};
    217
    218	sata3_pwr_pin: sata3-pwr-pin {
    219		marvell,pins = "mpp45";
    220		marvell,function = "gpio";
    221	};
    222
    223	sata4_pwr_pin: sata4-pwr-pin {
    224		marvell,pins = "mpp46";
    225		marvell,function = "gpio";
    226	};
    227
    228	sata1_pres_pin: sata1-pres-pin {
    229		marvell,pins = "mpp34";
    230		marvell,function = "gpio";
    231	};
    232
    233	sata2_pres_pin: sata2-pres-pin {
    234		marvell,pins = "mpp35";
    235		marvell,function = "gpio";
    236	};
    237
    238	sata3_pres_pin: sata3-pres-pin {
    239		marvell,pins = "mpp40";
    240		marvell,function = "gpio";
    241	};
    242
    243	sata4_pres_pin: sata4-pres-pin {
    244		marvell,pins = "mpp41";
    245		marvell,function = "gpio";
    246	};
    247
    248	syno_id_bit0_pin: syno-id-bit0-pin {
    249		marvell,pins = "mpp26";
    250		marvell,function = "gpio";
    251	};
    252
    253	syno_id_bit1_pin: syno-id-bit1-pin {
    254		marvell,pins = "mpp28";
    255		marvell,function = "gpio";
    256	};
    257
    258	syno_id_bit2_pin: syno-id-bit2-pin {
    259		marvell,pins = "mpp29";
    260		marvell,function = "gpio";
    261	};
    262
    263	fan1_alarm_pin: fan1-alarm-pin {
    264		marvell,pins = "mpp33";
    265		marvell,function = "gpio";
    266	};
    267
    268	fan2_alarm_pin: fan2-alarm-pin {
    269		marvell,pins = "mpp32";
    270		marvell,function = "gpio";
    271	};
    272};
    273
    274&spi0 {
    275	status = "okay";
    276
    277	flash@0 {
    278		#address-cells = <1>;
    279		#size-cells = <1>;
    280		compatible = "micron,n25q064", "jedec,spi-nor";
    281		reg = <0>; /* Chip select 0 */
    282		spi-max-frequency = <20000000>;
    283
    284		/*
    285		 * Warning!
    286		 *
    287		 * Synology u-boot uses its compiled-in environment
    288		 * and it seems Synology did not care to change u-boot
    289		 * default configuration in order to allow saving a
    290		 * modified environment at a sensible location. So,
    291		 * if you do a 'saveenv' under u-boot, your modified
    292		 * environment will be saved at 1MB after the start
    293		 * of the flash, i.e. in the middle of the uImage.
    294		 * For that reason, it is strongly advised not to
    295		 * change the default environment, unless you know
    296		 * what you are doing.
    297		 */
    298		partition@0 { /* u-boot */
    299			label = "RedBoot";
    300			reg = <0x00000000 0x000d0000>; /* 832KB */
    301		};
    302
    303		partition@c0000 { /* uImage */
    304			label = "zImage";
    305			reg = <0x000d0000 0x002d0000>; /* 2880KB */
    306		};
    307
    308		partition@3a0000 { /* uInitramfs */
    309			label = "rd.gz";
    310			reg = <0x003a0000 0x00430000>; /* 4250KB */
    311		};
    312
    313		partition@7d0000 { /* MAC address and serial number */
    314			label = "vendor";
    315			reg = <0x007d0000 0x00010000>; /* 64KB */
    316		};
    317
    318		partition@7e0000 {
    319			label = "RedBoot config";
    320			reg = <0x007e0000 0x00010000>; /* 64KB */
    321		};
    322
    323		partition@7f0000 {
    324			label = "FIS directory";
    325			reg = <0x007f0000 0x00010000>; /* 64KB */
    326		};
    327	};
    328};