aspeed-bmc-ampere-mtjade.dts (16943B)
1// SPDX-License-Identifier: GPL-2.0+ 2/dts-v1/; 3#include "aspeed-g5.dtsi" 4#include <dt-bindings/gpio/aspeed-gpio.h> 5 6/ { 7 model = "Ampere Mt. Jade BMC"; 8 compatible = "ampere,mtjade-bmc", "aspeed,ast2500"; 9 10 aliases { 11 /* 12 * i2c bus 50-57 assigned to NVMe slot 0-7 13 */ 14 i2c50 = &nvmeslot_0; 15 i2c51 = &nvmeslot_1; 16 i2c52 = &nvmeslot_2; 17 i2c53 = &nvmeslot_3; 18 i2c54 = &nvmeslot_4; 19 i2c55 = &nvmeslot_5; 20 i2c56 = &nvmeslot_6; 21 i2c57 = &nvmeslot_7; 22 23 /* 24 * i2c bus 60-67 assigned to NVMe slot 8-15 25 */ 26 i2c60 = &nvmeslot_8; 27 i2c61 = &nvmeslot_9; 28 i2c62 = &nvmeslot_10; 29 i2c63 = &nvmeslot_11; 30 i2c64 = &nvmeslot_12; 31 i2c65 = &nvmeslot_13; 32 i2c66 = &nvmeslot_14; 33 i2c67 = &nvmeslot_15; 34 35 /* 36 * i2c bus 70-77 assigned to NVMe slot 16-23 37 */ 38 i2c70 = &nvmeslot_16; 39 i2c71 = &nvmeslot_17; 40 i2c72 = &nvmeslot_18; 41 i2c73 = &nvmeslot_19; 42 i2c74 = &nvmeslot_20; 43 i2c75 = &nvmeslot_21; 44 i2c76 = &nvmeslot_22; 45 i2c77 = &nvmeslot_23; 46 47 /* 48 * i2c bus 80-81 assigned to NVMe M2 slot 0-1 49 */ 50 i2c80 = &nvme_m2_0; 51 i2c81 = &nvme_m2_1; 52 }; 53 54 chosen { 55 stdout-path = &uart5; 56 bootargs = "console=ttyS4,115200 earlycon"; 57 }; 58 59 memory@80000000 { 60 reg = <0x80000000 0x20000000>; 61 }; 62 63 reserved-memory { 64 #address-cells = <1>; 65 #size-cells = <1>; 66 ranges; 67 68 vga_memory: framebuffer@9f000000 { 69 no-map; 70 reg = <0x9f000000 0x01000000>; /* 16M */ 71 }; 72 73 gfx_memory: framebuffer { 74 size = <0x01000000>; 75 alignment = <0x01000000>; 76 compatible = "shared-dma-pool"; 77 reusable; 78 }; 79 80 video_engine_memory: jpegbuffer { 81 size = <0x02000000>; /* 32M */ 82 alignment = <0x01000000>; 83 compatible = "shared-dma-pool"; 84 reusable; 85 }; 86 }; 87 88 leds { 89 compatible = "gpio-leds"; 90 91 fault { 92 gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_HIGH>; 93 }; 94 95 identify { 96 gpios = <&gpio ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>; 97 }; 98 }; 99 100 gpio-keys { 101 compatible = "gpio-keys"; 102 103 shutdown_ack { 104 label = "SHUTDOWN_ACK"; 105 gpios = <&gpio ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>; 106 linux,code = <ASPEED_GPIO(G, 2)>; 107 }; 108 109 reboot_ack { 110 label = "REBOOT_ACK"; 111 gpios = <&gpio ASPEED_GPIO(J, 3) GPIO_ACTIVE_LOW>; 112 linux,code = <ASPEED_GPIO(J, 3)>; 113 }; 114 115 S0_overtemp { 116 label = "S0_OVERTEMP"; 117 gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>; 118 linux,code = <ASPEED_GPIO(G, 3)>; 119 }; 120 121 S0_hightemp { 122 label = "S0_HIGHTEMP"; 123 gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>; 124 linux,code = <ASPEED_GPIO(J, 0)>; 125 }; 126 127 S0_cpu_fault { 128 label = "S0_CPU_FAULT"; 129 gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>; 130 linux,code = <ASPEED_GPIO(J, 1)>; 131 }; 132 133 S0_scp_auth_fail { 134 label = "S0_SCP_AUTH_FAIL"; 135 gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; 136 linux,code = <ASPEED_GPIO(J, 2)>; 137 }; 138 139 S1_scp_auth_fail { 140 label = "S1_SCP_AUTH_FAIL"; 141 gpios = <&gpio ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>; 142 linux,code = <ASPEED_GPIO(Z, 5)>; 143 }; 144 145 S1_overtemp { 146 label = "S1_OVERTEMP"; 147 gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>; 148 linux,code = <ASPEED_GPIO(Z, 6)>; 149 }; 150 151 S1_hightemp { 152 label = "S1_HIGHTEMP"; 153 gpios = <&gpio ASPEED_GPIO(AB, 0) GPIO_ACTIVE_LOW>; 154 linux,code = <ASPEED_GPIO(AB, 0)>; 155 }; 156 157 S1_cpu_fault { 158 label = "S1_CPU_FAULT"; 159 gpios = <&gpio ASPEED_GPIO(Z, 1) GPIO_ACTIVE_HIGH>; 160 linux,code = <ASPEED_GPIO(Z, 1)>; 161 }; 162 163 id_button { 164 label = "ID_BUTTON"; 165 gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; 166 linux,code = <ASPEED_GPIO(Q, 5)>; 167 }; 168 169 psu1_vin_good { 170 label = "PSU1_VIN_GOOD"; 171 gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; 172 linux,code = <ASPEED_GPIO(H, 4)>; 173 }; 174 175 psu2_vin_good { 176 label = "PSU2_VIN_GOOD"; 177 gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>; 178 linux,code = <ASPEED_GPIO(H, 5)>; 179 }; 180 181 psu1_present { 182 label = "PSU1_PRESENT"; 183 gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; 184 linux,code = <ASPEED_GPIO(I, 0)>; 185 }; 186 187 psu2_present { 188 label = "PSU2_PRESENT"; 189 gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; 190 linux,code = <ASPEED_GPIO(I, 1)>; 191 }; 192 193 }; 194 195 gpioA0mux: mux-controller { 196 compatible = "gpio-mux"; 197 #mux-control-cells = <0>; 198 mux-gpios = <&gpio ASPEED_GPIO(A, 0) GPIO_ACTIVE_LOW>; 199 }; 200 201 adc0mux: adc0mux { 202 compatible = "io-channel-mux"; 203 io-channels = <&adc 0>; 204 #io-channel-cells = <1>; 205 io-channel-names = "parent"; 206 mux-controls = <&gpioA0mux>; 207 channels = "s0", "s1"; 208 }; 209 210 adc1mux: adc1mux { 211 compatible = "io-channel-mux"; 212 io-channels = <&adc 1>; 213 #io-channel-cells = <1>; 214 io-channel-names = "parent"; 215 mux-controls = <&gpioA0mux>; 216 channels = "s0", "s1"; 217 }; 218 219 adc2mux: adc2mux { 220 compatible = "io-channel-mux"; 221 io-channels = <&adc 2>; 222 #io-channel-cells = <1>; 223 io-channel-names = "parent"; 224 mux-controls = <&gpioA0mux>; 225 channels = "s0", "s1"; 226 }; 227 228 adc3mux: adc3mux { 229 compatible = "io-channel-mux"; 230 io-channels = <&adc 3>; 231 #io-channel-cells = <1>; 232 io-channel-names = "parent"; 233 mux-controls = <&gpioA0mux>; 234 channels = "s0", "s1"; 235 }; 236 237 adc4mux: adc4mux { 238 compatible = "io-channel-mux"; 239 io-channels = <&adc 4>; 240 #io-channel-cells = <1>; 241 io-channel-names = "parent"; 242 mux-controls = <&gpioA0mux>; 243 channels = "s0", "s1"; 244 }; 245 246 adc5mux: adc5mux { 247 compatible = "io-channel-mux"; 248 io-channels = <&adc 5>; 249 #io-channel-cells = <1>; 250 io-channel-names = "parent"; 251 mux-controls = <&gpioA0mux>; 252 channels = "s0", "s1"; 253 }; 254 255 adc6mux: adc6mux { 256 compatible = "io-channel-mux"; 257 io-channels = <&adc 6>; 258 #io-channel-cells = <1>; 259 io-channel-names = "parent"; 260 mux-controls = <&gpioA0mux>; 261 channels = "s0", "s1"; 262 }; 263 264 adc7mux: adc7mux { 265 compatible = "io-channel-mux"; 266 io-channels = <&adc 7>; 267 #io-channel-cells = <1>; 268 io-channel-names = "parent"; 269 mux-controls = <&gpioA0mux>; 270 channels = "s0", "s1"; 271 }; 272 273 adc8mux: adc8mux { 274 compatible = "io-channel-mux"; 275 io-channels = <&adc 8>; 276 #io-channel-cells = <1>; 277 io-channel-names = "parent"; 278 mux-controls = <&gpioA0mux>; 279 channels = "s0", "s1"; 280 }; 281 282 adc9mux: adc9mux { 283 compatible = "io-channel-mux"; 284 io-channels = <&adc 9>; 285 #io-channel-cells = <1>; 286 io-channel-names = "parent"; 287 mux-controls = <&gpioA0mux>; 288 channels = "s0", "s1"; 289 }; 290 291 adc10mux: adc10mux { 292 compatible = "io-channel-mux"; 293 io-channels = <&adc 10>; 294 #io-channel-cells = <1>; 295 io-channel-names = "parent"; 296 mux-controls = <&gpioA0mux>; 297 channels = "s0", "s1"; 298 }; 299 300 adc11mux: adc11mux { 301 compatible = "io-channel-mux"; 302 io-channels = <&adc 11>; 303 #io-channel-cells = <1>; 304 io-channel-names = "parent"; 305 mux-controls = <&gpioA0mux>; 306 channels = "s0", "s1"; 307 }; 308 309 adc12mux: adc12mux { 310 compatible = "io-channel-mux"; 311 io-channels = <&adc 12>; 312 #io-channel-cells = <1>; 313 io-channel-names = "parent"; 314 mux-controls = <&gpioA0mux>; 315 channels = "s0", "s1"; 316 }; 317 318 adc13mux: adc13mux { 319 compatible = "io-channel-mux"; 320 io-channels = <&adc 13>; 321 #io-channel-cells = <1>; 322 io-channel-names = "parent"; 323 mux-controls = <&gpioA0mux>; 324 channels = "s0", "s1"; 325 }; 326 327 iio-hwmon { 328 compatible = "iio-hwmon"; 329 io-channels = <&adc0mux 0>, <&adc0mux 1>, 330 <&adc1mux 0>, <&adc1mux 1>, 331 <&adc2mux 0>, <&adc2mux 1>, 332 <&adc3mux 0>, <&adc3mux 1>, 333 <&adc4mux 0>, <&adc4mux 1>, 334 <&adc5mux 0>, <&adc5mux 1>, 335 <&adc6mux 0>, <&adc6mux 1>, 336 <&adc7mux 0>, <&adc7mux 1>, 337 <&adc8mux 0>, <&adc8mux 1>, 338 <&adc9mux 0>, <&adc9mux 1>, 339 <&adc10mux 0>, <&adc10mux 1>, 340 <&adc11mux 0>, <&adc11mux 1>, 341 <&adc12mux 0>, <&adc12mux 1>, 342 <&adc13mux 0>, <&adc13mux 1>, 343 <&adc 14>, <&adc 15>; 344 }; 345}; 346 347&fmc { 348 status = "okay"; 349 flash@0 { 350 status = "okay"; 351 m25p,fast-read; 352 label = "bmc"; 353 /* spi-max-frequency = <50000000>; */ 354#include "openbmc-flash-layout-64.dtsi" 355 }; 356 357 flash@1 { 358 status = "okay"; 359 m25p,fast-read; 360 label = "alt-bmc"; 361#include "openbmc-flash-layout-64-alt.dtsi" 362 }; 363}; 364 365&spi1 { 366 status = "okay"; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pinctrl_spi1_default>; 369 370 flash@0 { 371 status = "okay"; 372 m25p,fast-read; 373 label = "pnor"; 374 /* spi-max-frequency = <100000000>; */ 375 partitions { 376 compatible = "fixed-partitions"; 377 #address-cells = <1>; 378 #size-cells = <1>; 379 uefi@400000 { 380 reg = <0x400000 0x1C00000>; 381 label = "pnor-uefi"; 382 }; 383 }; 384 }; 385}; 386 387&uart1 { 388 status = "okay"; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&pinctrl_txd1_default 391 &pinctrl_rxd1_default 392 &pinctrl_ncts1_default 393 &pinctrl_nrts1_default>; 394}; 395 396&uart2 { 397 status = "okay"; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&pinctrl_txd2_default 400 &pinctrl_rxd2_default>; 401}; 402 403&uart3 { 404 status = "okay"; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&pinctrl_txd3_default 407 &pinctrl_rxd3_default>; 408}; 409 410&uart4 { 411 status = "okay"; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&pinctrl_txd4_default 414 &pinctrl_rxd4_default>; 415}; 416 417/* The BMC's uart */ 418&uart5 { 419 status = "okay"; 420}; 421 422&mac0 { 423 status = "okay"; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&pinctrl_rmii1_default>; 426 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, 427 <&syscon ASPEED_CLK_MAC1RCLK>; 428 clock-names = "MACCLK", "RCLK"; 429 use-ncsi; 430}; 431 432&mac1 { 433 status = "okay"; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; 436}; 437 438&i2c0 { 439 status = "okay"; 440}; 441 442&i2c1 { 443 status = "okay"; 444}; 445 446&i2c2 { 447 status = "okay"; 448}; 449 450&i2c3 { 451 status = "okay"; 452 eeprom@50 { 453 compatible = "microchip,24c64", "atmel,24c64"; 454 reg = <0x50>; 455 pagesize = <32>; 456 }; 457 458 inlet_mem2: tmp175@28 { 459 compatible = "ti,tmp175"; 460 reg = <0x28>; 461 }; 462 463 inlet_cpu: tmp175@29 { 464 compatible = "ti,tmp175"; 465 reg = <0x29>; 466 }; 467 468 inlet_mem1: tmp175@2a { 469 compatible = "ti,tmp175"; 470 reg = <0x2a>; 471 }; 472 473 outlet_cpu: tmp175@2b { 474 compatible = "ti,tmp175"; 475 reg = <0x2b>; 476 }; 477 478 outlet1: tmp175@2c { 479 compatible = "ti,tmp175"; 480 reg = <0x2c>; 481 }; 482 483 outlet2: tmp175@2d { 484 compatible = "ti,tmp175"; 485 reg = <0x2d>; 486 }; 487}; 488 489&i2c4 { 490 status = "okay"; 491 rtc@51 { 492 compatible = "nxp,pcf85063a"; 493 reg = <0x51>; 494 }; 495}; 496 497&i2c5 { 498 status = "okay"; 499 i2c-mux@70 { 500 compatible = "nxp,pca9548"; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 reg = <0x70>; 504 i2c-mux-idle-disconnect; 505 506 nvmeslot_0_7: i2c@3 { 507 #address-cells = <1>; 508 #size-cells = <0>; 509 reg = <0x3>; 510 }; 511 }; 512 513 i2c-mux@71 { 514 compatible = "nxp,pca9548"; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 reg = <0x71>; 518 i2c-mux-idle-disconnect; 519 520 nvmeslot_8_15: i2c@4 { 521 #address-cells = <1>; 522 #size-cells = <0>; 523 reg = <0x4>; 524 }; 525 526 nvmeslot_16_23: i2c@3 { 527 #address-cells = <1>; 528 #size-cells = <0>; 529 reg = <0x3>; 530 }; 531 532 }; 533 534 i2c-mux@72 { 535 compatible = "nxp,pca9545"; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 reg = <0x72>; 539 i2c-mux-idle-disconnect; 540 541 nvme_m2_0: i2c@0 { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 reg = <0x0>; 545 }; 546 547 nvme_m2_1: i2c@1 { 548 #address-cells = <1>; 549 #size-cells = <0>; 550 reg = <0x1>; 551 }; 552 }; 553}; 554 555&nvmeslot_0_7 { 556 status = "okay"; 557 558 i2c-mux@75 { 559 compatible = "nxp,pca9548"; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 reg = <0x75>; 563 i2c-mux-idle-disconnect; 564 565 nvmeslot_0: i2c@0 { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 reg = <0x0>; 569 }; 570 nvmeslot_1: i2c@1 { 571 #address-cells = <1>; 572 #size-cells = <0>; 573 reg = <0x1>; 574 }; 575 nvmeslot_2: i2c@2 { 576 #address-cells = <1>; 577 #size-cells = <0>; 578 reg = <0x2>; 579 }; 580 nvmeslot_3: i2c@3 { 581 #address-cells = <1>; 582 #size-cells = <0>; 583 reg = <0x3>; 584 }; 585 nvmeslot_4: i2c@4 { 586 #address-cells = <1>; 587 #size-cells = <0>; 588 reg = <0x4>; 589 }; 590 nvmeslot_5: i2c@5 { 591 #address-cells = <1>; 592 #size-cells = <0>; 593 reg = <0x5>; 594 }; 595 nvmeslot_6: i2c@6 { 596 #address-cells = <1>; 597 #size-cells = <0>; 598 reg = <0x6>; 599 }; 600 nvmeslot_7: i2c@7 { 601 #address-cells = <1>; 602 #size-cells = <0>; 603 reg = <0x7>; 604 }; 605 606 }; 607}; 608 609&nvmeslot_8_15 { 610 status = "okay"; 611 612 i2c-mux@75 { 613 compatible = "nxp,pca9548"; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 reg = <0x75>; 617 i2c-mux-idle-disconnect; 618 619 nvmeslot_8: i2c@0 { 620 #address-cells = <1>; 621 #size-cells = <0>; 622 reg = <0x0>; 623 }; 624 nvmeslot_9: i2c@1 { 625 #address-cells = <1>; 626 #size-cells = <0>; 627 reg = <0x1>; 628 }; 629 nvmeslot_10: i2c@2 { 630 #address-cells = <1>; 631 #size-cells = <0>; 632 reg = <0x2>; 633 }; 634 nvmeslot_11: i2c@3 { 635 #address-cells = <1>; 636 #size-cells = <0>; 637 reg = <0x3>; 638 }; 639 nvmeslot_12: i2c@4 { 640 #address-cells = <1>; 641 #size-cells = <0>; 642 reg = <0x4>; 643 }; 644 nvmeslot_13: i2c@5 { 645 #address-cells = <1>; 646 #size-cells = <0>; 647 reg = <0x5>; 648 }; 649 nvmeslot_14: i2c@6 { 650 #address-cells = <1>; 651 #size-cells = <0>; 652 reg = <0x6>; 653 }; 654 nvmeslot_15: i2c@7 { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 reg = <0x7>; 658 }; 659 }; 660}; 661 662&nvmeslot_16_23 { 663 status = "okay"; 664 665 i2c-mux@75 { 666 compatible = "nxp,pca9548"; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 reg = <0x75>; 670 i2c-mux-idle-disconnect; 671 672 nvmeslot_16: i2c@0 { 673 #address-cells = <1>; 674 #size-cells = <0>; 675 reg = <0x0>; 676 }; 677 nvmeslot_17: i2c@1 { 678 #address-cells = <1>; 679 #size-cells = <0>; 680 reg = <0x1>; 681 }; 682 nvmeslot_18: i2c@2 { 683 #address-cells = <1>; 684 #size-cells = <0>; 685 reg = <0x2>; 686 }; 687 nvmeslot_19: i2c@3 { 688 #address-cells = <1>; 689 #size-cells = <0>; 690 reg = <0x3>; 691 }; 692 nvmeslot_20: i2c@4 { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 reg = <0x4>; 696 }; 697 nvmeslot_21: i2c@5 { 698 #address-cells = <1>; 699 #size-cells = <0>; 700 reg = <0x5>; 701 }; 702 nvmeslot_22: i2c@6 { 703 #address-cells = <1>; 704 #size-cells = <0>; 705 reg = <0x6>; 706 }; 707 nvmeslot_23: i2c@7 { 708 #address-cells = <1>; 709 #size-cells = <0>; 710 reg = <0x7>; 711 }; 712 }; 713}; 714 715&i2c6 { 716 status = "okay"; 717 psu@58 { 718 compatible = "pmbus"; 719 reg = <0x58>; 720 }; 721 722 psu@59 { 723 compatible = "pmbus"; 724 reg = <0x59>; 725 }; 726}; 727 728&i2c7 { 729 status = "okay"; 730}; 731 732&i2c8 { 733 status = "okay"; 734}; 735 736&i2c9 { 737 status = "okay"; 738}; 739 740&i2c10 { 741 status = "okay"; 742 adm1278@10 { 743 compatible = "adi,adm1278"; 744 reg = <0x10>; 745 }; 746 747 adm1278@11 { 748 compatible = "adi,adm1278"; 749 reg = <0x11>; 750 }; 751}; 752 753&gfx { 754 status = "okay"; 755 memory-region = <&gfx_memory>; 756}; 757 758&pinctrl { 759 aspeed,external-nodes = <&gfx &lhc>; 760}; 761 762&pwm_tacho { 763 status = "okay"; 764 pinctrl-names = "default"; 765 pinctrl-0 = <&pinctrl_pwm2_default &pinctrl_pwm3_default 766 &pinctrl_pwm4_default &pinctrl_pwm5_default 767 &pinctrl_pwm6_default &pinctrl_pwm7_default>; 768 769 fan@0 { 770 reg = <0x02>; 771 aspeed,fan-tach-ch = /bits/ 8 <0x04>; 772 }; 773 774 fan@1 { 775 reg = <0x02>; 776 aspeed,fan-tach-ch = /bits/ 8 <0x05>; 777 }; 778 779 fan@2 { 780 reg = <0x03>; 781 aspeed,fan-tach-ch = /bits/ 8 <0x06>; 782 }; 783 784 fan@3 { 785 reg = <0x03>; 786 aspeed,fan-tach-ch = /bits/ 8 <0x07>; 787 }; 788 789 fan@4 { 790 reg = <0x04>; 791 aspeed,fan-tach-ch = /bits/ 8 <0x08>; 792 }; 793 794 fan@5 { 795 reg = <0x04>; 796 aspeed,fan-tach-ch = /bits/ 8 <0x09>; 797 }; 798 799 fan@6 { 800 reg = <0x05>; 801 aspeed,fan-tach-ch = /bits/ 8 <0x0a>; 802 }; 803 804 fan@7 { 805 reg = <0x05>; 806 aspeed,fan-tach-ch = /bits/ 8 <0x0b>; 807 }; 808 809 fan@8 { 810 reg = <0x06>; 811 aspeed,fan-tach-ch = /bits/ 8 <0x0c>; 812 }; 813 814 fan@9 { 815 reg = <0x06>; 816 aspeed,fan-tach-ch = /bits/ 8 <0x0d>; 817 }; 818 819 fan@10 { 820 reg = <0x07>; 821 aspeed,fan-tach-ch = /bits/ 8 <0x0e>; 822 }; 823 824 fan@11 { 825 reg = <0x07>; 826 aspeed,fan-tach-ch = /bits/ 8 <0x0f>; 827 }; 828 829}; 830 831&vhub { 832 status = "okay"; 833}; 834 835&adc { 836 status = "okay"; 837}; 838 839&video { 840 status = "okay"; 841 memory-region = <&video_engine_memory>; 842}; 843 844&gpio { 845 gpio-line-names = 846 /*A0-A7*/ "","","","S0_BMC_SPECIAL_BOOT","","","","", 847 /*B0-B7*/ "BMC_SELECT_EEPROM","","","", 848 "POWER_BUTTON","","","", 849 /*C0-C7*/ "","","","","","","","", 850 /*D0-D7*/ "","","","","","","","", 851 /*E0-E7*/ "","","","","","","","", 852 /*F0-F7*/ "","","BMC_SYS_PSON_L","S0_DDR_SAVE","PGOOD", 853 "S1_DDR_SAVE","","", 854 /*G0-G7*/ "host0-ready","SHD_REQ_L","","S0_OVERTEMP_L","","", 855 "","", 856 /*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","", 857 /*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT", 858 "","","","","", 859 /*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","", 860 "","","","", 861 /*K0-K7*/ "","","","","","","","", 862 /*L0-L7*/ "","","","BMC_SYSRESET_L","SPI_AUTH_FAIL_L","","","", 863 /*M0-M7*/ "","","","","","","","", 864 /*N0-N7*/ "","","","","","","","", 865 /*O0-O7*/ "","","","","","","","", 866 /*P0-P7*/ "","","","","","","","", 867 /*Q0-Q7*/ "","","","","","UID_BUTTON","","", 868 /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", 869 "OCP_MAIN_PWREN","RESET_BUTTON","","", 870 /*S0-S7*/ "","","","","rtc-battery-voltage-read-enable","","","", 871 /*T0-T7*/ "","","","","","","","", 872 /*U0-U7*/ "","","","","","","","", 873 /*V0-V7*/ "","","","","","","","", 874 /*W0-W7*/ "","","","","","","","", 875 /*X0-X7*/ "","","","","","","","", 876 /*Y0-Y7*/ "","","","","","","","", 877 /*Z0-Z7*/ "S0_BMC_PLIMIT","S1_FAULT_L","S1_FW_BOOT_OK","","", 878 "S1_SCP_AUTH_FAIL_L","S1_OVERTEMP_L","", 879 /*AA0-AA7*/ "","","","","","","","", 880 /*AB0-AB7*/ "S1_HIGHTEMP_L","S1_BMC_PLIMIT","S0_BMC_DDR_ADDR", 881 "S1_BMC_DDR_ADR","","","","", 882 /*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L", 883 "BMC_OCP_PG"; 884 885 i2c4-o-en-hog { 886 gpio-hog; 887 gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>; 888 output-high; 889 line-name = "BMC_I2C4_O_EN"; 890 }; 891};