cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

aspeed-bmc-facebook-yosemitev2.dts (3781B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2// Copyright (c) 2018 Facebook Inc.
      3/dts-v1/;
      4#include "aspeed-g5.dtsi"
      5#include <dt-bindings/i2c/i2c.h>
      6
      7/ {
      8	model = "Facebook Yosemitev2 BMC";
      9	compatible = "facebook,yosemitev2-bmc", "aspeed,ast2500";
     10	aliases {
     11		serial4 = &uart5;
     12	};
     13	chosen {
     14		stdout-path = &uart5;
     15	};
     16
     17	memory@80000000 {
     18		reg = <0x80000000 0x20000000>;
     19	};
     20
     21	iio-hwmon {
     22		// VOLATAGE SENSOR
     23		compatible = "iio-hwmon";
     24		io-channels = <&adc 0> , <&adc 1> , <&adc 2> ,  <&adc 3> ,
     25		<&adc 4> , <&adc 5> , <&adc 6> ,  <&adc 7> ,
     26		<&adc 8> , <&adc 9> , <&adc 10>, <&adc 11> ,
     27		<&adc 12> , <&adc 13> , <&adc 14> , <&adc 15> ;
     28	};
     29};
     30
     31&fmc {
     32	status = "okay";
     33	flash@0 {
     34		status = "okay";
     35		m25p,fast-read;
     36#include "openbmc-flash-layout.dtsi"
     37	};
     38};
     39
     40&spi1 {
     41	status = "okay";
     42	pinctrl-names = "default";
     43	pinctrl-0 = <&pinctrl_spi1_default>;
     44	flash@0 {
     45		status = "okay";
     46		m25p,fast-read;
     47		label = "pnor";
     48	};
     49};
     50&uart1 {
     51	// Host1 Console
     52	status = "okay";
     53	pinctrl-names = "default";
     54	pinctrl-0 = <&pinctrl_txd1_default
     55		     &pinctrl_rxd1_default>;
     56};
     57
     58&uart2 {
     59	// Host2 Console
     60	status = "okay";
     61	pinctrl-names = "default";
     62	pinctrl-0 = <&pinctrl_txd2_default
     63		     &pinctrl_rxd2_default>;
     64
     65};
     66
     67&uart3 {
     68	// Host3 Console
     69	status = "okay";
     70	pinctrl-names = "default";
     71	pinctrl-0 = <&pinctrl_txd3_default
     72		     &pinctrl_rxd3_default>;
     73};
     74
     75&uart4 {
     76	// Host4 Console
     77	status = "okay";
     78	pinctrl-names = "default";
     79	pinctrl-0 = <&pinctrl_txd4_default
     80		     &pinctrl_rxd4_default>;
     81};
     82
     83&uart5 {
     84	// BMC Console
     85	status = "okay";
     86};
     87
     88&vuart {
     89	// Virtual UART
     90	status = "okay";
     91};
     92
     93&mac0 {
     94	status = "okay";
     95	pinctrl-names = "default";
     96	pinctrl-0 = <&pinctrl_rmii1_default>;
     97	use-ncsi;
     98	mlx,multi-host;
     99};
    100
    101&adc {
    102	status = "okay";
    103	pinctrl-names = "default";
    104	pinctrl-0 = <&pinctrl_adc0_default
    105			&pinctrl_adc1_default
    106			&pinctrl_adc2_default
    107			&pinctrl_adc3_default
    108			&pinctrl_adc4_default
    109			&pinctrl_adc5_default
    110			&pinctrl_adc6_default
    111			&pinctrl_adc7_default
    112			&pinctrl_adc8_default
    113			&pinctrl_adc9_default
    114			&pinctrl_adc10_default
    115			&pinctrl_adc11_default
    116			&pinctrl_adc12_default
    117			&pinctrl_adc13_default
    118			&pinctrl_adc14_default
    119			&pinctrl_adc15_default>;
    120};
    121
    122&i2c1 {
    123	//Host1 IPMB bus
    124	status = "okay";
    125	multi-master;
    126	ipmb1@10 {
    127		compatible = "ipmb-dev";
    128		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
    129		i2c-protocol;
    130	};
    131};
    132
    133&i2c3 {
    134	//Host2 IPMB bus
    135	status = "okay";
    136	multi-master;
    137	ipmb3@10 {
    138		compatible = "ipmb-dev";
    139		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
    140		i2c-protocol;
    141	};
    142};
    143
    144&i2c5 {
    145	//Host3 IPMB bus
    146	status = "okay";
    147	multi-master;
    148	ipmb5@10 {
    149		compatible = "ipmb-dev";
    150		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
    151		i2c-protocol;
    152	};
    153};
    154
    155&i2c7 {
    156	//Host4 IPMB bus
    157	status = "okay";
    158	multi-master;
    159	ipmb7@10 {
    160		compatible = "ipmb-dev";
    161		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
    162		i2c-protocol;
    163	};
    164};
    165
    166&i2c8 {
    167	status = "okay";
    168	//FRU EEPROM
    169	eeprom@51 {
    170		compatible = "atmel,24c64";
    171		reg = <0x51>;
    172		pagesize = <32>;
    173	};
    174};
    175
    176&i2c9 {
    177	status = "okay";
    178	tmp421@4e {
    179	//INLET TEMP
    180		compatible = "ti,tmp421";
    181		reg = <0x4e>;
    182	};
    183	//OUTLET TEMP
    184	tmp421@4f {
    185		compatible = "ti,tmp421";
    186		reg = <0x4f>;
    187	};
    188};
    189
    190&i2c10 {
    191	status = "okay";
    192	//HSC
    193	adm1278@40 {
    194		compatible = "adi,adm1278";
    195		reg = <0x40>;
    196	};
    197};
    198
    199&i2c11 {
    200	status = "okay";
    201	//MEZZ_TEMP_SENSOR
    202	tmp421@1f {
    203		compatible = "ti,tmp421";
    204		reg = <0x1f>;
    205	};
    206};
    207
    208&i2c12 {
    209	status = "okay";
    210	//MEZZ_FRU
    211	eeprom@51 {
    212		compatible = "atmel,24c64";
    213		reg = <0x51>;
    214		pagesize = <32>;
    215	};
    216};
    217
    218&pwm_tacho {
    219	status = "okay";
    220	//FSC
    221	pinctrl-names = "default";
    222	pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
    223	fan@0 {
    224		reg = <0x00>;
    225		aspeed,fan-tach-ch = /bits/ 8 <0x00>;
    226	};
    227	fan@1 {
    228		reg = <0x01>;
    229		aspeed,fan-tach-ch = /bits/ 8 <0x01>;
    230	};
    231};