cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

aspeed-bmc-portwell-neptune.dts (2739B)

      1// SPDX-License-Identifier: GPL-2.0
      2// Copyright (c) 2017 Facebook Inc.
      3/dts-v1/;
      4
      5#include "aspeed-g5.dtsi"
      6#include <dt-bindings/gpio/aspeed-gpio.h>
      7
      8/ {
      9	model = "Portwell Neptune BMC";
     10	compatible = "portwell,neptune-bmc", "aspeed,ast2500";
     11	aliases {
     12		serial0 = &uart1;
     13		serial4 = &uart5;
     14	};
     15	chosen {
     16		stdout-path = &uart5;
     17		bootargs = "console=ttyS4,115200 earlycon";
     18	};
     19
     20	memory@80000000 {
     21		reg = <0x80000000 0x20000000>;
     22	};
     23
     24	leds {
     25		compatible = "gpio-leds";
     26		postcode0 {
     27			label="BMC_UP";
     28			gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
     29			default-state = "on";
     30		};
     31		postcode1 {
     32			label="BMC_HB";
     33			gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
     34			linux,default-trigger = "heartbeat";
     35		};
     36		postcode2 {
     37			label="FAULT";
     38			gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
     39		};
     40		// postcode3-7 are GPIOH3-H7
     41	};
     42};
     43
     44&fmc {
     45	status = "okay";
     46	flash@0 {
     47		status = "okay";
     48		m25p,fast-read;
     49#include "openbmc-flash-layout.dtsi"
     50	};
     51};
     52
     53&spi1 {
     54	status = "okay";
     55	pinctrl-names = "default";
     56	pinctrl-0 = <&pinctrl_spi1_default>;
     57	flash@0 {
     58		status = "okay";
     59		m25p,fast-read;
     60		label = "pnor";
     61	};
     62};
     63
     64&uart1 {
     65	// Host Console
     66	status = "okay";
     67	pinctrl-names = "default";
     68	pinctrl-0 = <&pinctrl_txd1_default
     69		     &pinctrl_rxd1_default>;
     70};
     71
     72&uart5 {
     73	// BMC Console
     74	status = "okay";
     75};
     76
     77&mac0 {
     78	status = "okay";
     79
     80	pinctrl-names = "default";
     81	pinctrl-0 = <&pinctrl_rmii1_default
     82		     &pinctrl_mdio1_default>;
     83	clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
     84		 <&syscon ASPEED_CLK_MAC1RCLK>;
     85	clock-names = "MACCLK", "RCLK";
     86};
     87
     88&mac1 {
     89	status = "okay";
     90	pinctrl-names = "default";
     91	pinctrl-0 = <&pinctrl_rmii2_default>;
     92	clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>,
     93		 <&syscon ASPEED_CLK_MAC2RCLK>;
     94	clock-names = "MACCLK", "RCLK";
     95	use-ncsi;
     96};
     97
     98&i2c1 {
     99	status = "okay";
    100	// To PCIe slot SMBUS
    101};
    102
    103&i2c2 {
    104	status = "okay";
    105	// To LAN I210
    106};
    107
    108&i2c3 {
    109	status = "okay";
    110	// SMBus to COMe AB
    111};
    112
    113&i2c4 {
    114	status = "okay";
    115	// I2C to COMe AB
    116};
    117
    118&i2c5 {
    119	status = "okay";
    120// 	USB Debug card
    121	pca9555@27 {
    122		compatible = "nxp,pca9555";
    123		reg = <0x27>;
    124		gpio-controller;
    125		#gpio-cells = <2>;
    126	};
    127};
    128
    129&i2c6 {
    130	status = "okay";
    131	tpm@20 {
    132		compatible = "infineon,slb9645tt";
    133		reg = <0x20>;
    134	};
    135	tmp421@4e {
    136		compatible = "ti,tmp421";
    137		reg = <0x4e>;
    138	};
    139	tmp421@4f {
    140		compatible = "ti,tmp421";
    141		reg = <0x4f>;
    142	};
    143};
    144
    145&i2c8 {
    146	status = "okay";
    147	eeprom@51 {
    148		compatible = "atmel,24c128";
    149		reg = <0x51>;
    150		pagesize = <32>;
    151	};
    152};
    153
    154&pwm_tacho {
    155	status = "okay";
    156	pinctrl-names = "default";
    157	pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
    158	fan@0 {
    159		reg = <0x00>;
    160		aspeed,fan-tach-ch = /bits/ 8 <0x00>;
    161	};
    162
    163	fan@1 {
    164		reg = <0x00>;
    165		aspeed,fan-tach-ch = /bits/ 8 <0x01>;
    166	};
    167};