cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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at91-lmu5000.dts (2362B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Device Tree file for CalAmp LMU5000 board
      4 *
      5 * Copyright (C) 2013 Adam Porter <porter.adam@gmail.com>
      6 */
      7
      8/dts-v1/;
      9#include "at91sam9g20.dtsi"
     10
     11/ {
     12	model = "CalAmp LMU5000";
     13	compatible = "calamp,lmu5000", "atmel,at91sam9g20", "atmel,at91sam9";
     14
     15	chosen {
     16		bootargs = "mem=64M console=ttyS0,115200 rootfstype=jffs2";
     17	};
     18
     19	memory {
     20		reg = <0x20000000 0x4000000>;
     21	};
     22
     23	clocks {
     24		#address-cells = <1>;
     25		#size-cells = <1>;
     26		ranges;
     27
     28		main_clock: clock@0 {
     29			compatible = "atmel,osc", "fixed-clock";
     30			clock-frequency = <18432000>;
     31		};
     32	};
     33};
     34
     35&dbgu {
     36	status = "okay";
     37};
     38
     39&ebi {
     40	status = "okay";
     41
     42	nand_controller: nand-controller {
     43		pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
     44		pinctrl-names = "default";
     45		status = "okay";
     46
     47		nand@3 {
     48			reg = <0x3 0x0 0x800000>;
     49			rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
     50			cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
     51			nand-bus-width = <8>;
     52			nand-ecc-mode = "soft";
     53			nand-on-flash-bbt;
     54			label = "atmel_nand";
     55			status = "okay";
     56
     57			partitions {
     58				compatible = "fixed-partitions";
     59				#address-cells = <1>;
     60				#size-cells = <1>;
     61
     62				kernel@0 {
     63					label = "kernel";
     64					reg = <0x0 0x400000>;
     65				};
     66
     67				rootfs@400000 {
     68					label = "rootfs";
     69					reg = <0x400000 0x3C00000>;
     70				};
     71
     72				user1@4000000 {
     73					label = "user1";
     74					reg = <0x4000000 0x2000000>;
     75				};
     76
     77				user2@6000000 {
     78					label = "user2";
     79					reg = <0x6000000 0x2000000>;
     80				};
     81			};
     82		};
     83	};
     84};
     85
     86&macb0 {
     87	phy-mode = "mii";
     88	status = "okay";
     89};
     90
     91&pinctrl {
     92	board {
     93		pinctrl_pck0_as_mck: pck0_as_mck {
     94			atmel,pins = <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
     95		};
     96	};
     97
     98	usb0 {
     99		pinctrl_usb1_vbus_gpio: usb0_vbus_gpio {
    100			atmel,pins = <AT91_PIOC 5 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
    101		};
    102	};
    103};
    104
    105&ssc0 {
    106	status = "okay";
    107	pinctrl-0 = <&pinctrl_ssc0_tx>;
    108};
    109
    110&uart0 {
    111	status = "okay";
    112};
    113
    114&uart1 {
    115	status = "okay";
    116};
    117
    118&usart0 {
    119	pinctrl-0 =
    120		<&pinctrl_usart0
    121		 &pinctrl_usart0_rts
    122		 &pinctrl_usart0_cts
    123		 &pinctrl_usart0_dtr_dsr
    124		 &pinctrl_usart0_dcd
    125		 &pinctrl_usart0_ri>;
    126	status = "okay";
    127};
    128
    129&usart2 {
    130	status = "okay";
    131};
    132
    133&usb0 {
    134	num-ports = <2>;
    135	status = "okay";
    136};
    137
    138&usb1 {
    139	pinctrl-names = "default";
    140	pinctrl-0 = <&pinctrl_usb1_vbus_gpio>;
    141	atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
    142	status = "okay";
    143};
    144
    145&watchdog {
    146	status = "okay";
    147};