cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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at91-q5xr5.dts (3218B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Device Tree file for Exegin Q5xR5 board
      4 *
      5 * Copyright (C) 2014 Owen Kirby <osk@exegin.com>
      6 */
      7
      8/dts-v1/;
      9#include "at91sam9g20.dtsi"
     10
     11/ {
     12	model = "Exegin Q5x (rev5)";
     13	compatible = "exegin,q5xr5", "atmel,at91sam9g20", "atmel,at91sam9";
     14
     15	chosen {
     16		bootargs = "console=ttyS0,115200 rootfstype=squashfs,jffs2";
     17	};
     18
     19	memory {
     20		reg = <0x20000000 0x0>;
     21	};
     22
     23	clocks {
     24		#address-cells = <1>;
     25		#size-cells = <1>;
     26		ranges;
     27
     28		main_clock: clock@0 {
     29			compatible = "atmel,osc", "fixed-clock";
     30			clock-frequency = <18432000>;
     31		};
     32
     33		slow_xtal {
     34			clock-frequency = <32768>;
     35		};
     36
     37		main_xtal {
     38			clock-frequency = <18432000>;
     39		};
     40	};
     41};
     42
     43&dbgu {
     44	status = "okay";
     45};
     46
     47&ebi {
     48	status = "okay";
     49
     50	flash: flash@0 {
     51		compatible = "cfi-flash";
     52		#address-cells = <1>;
     53		#size-cells = <1>;
     54		reg = <0x0 0x1000000 0x800000>;
     55		bank-width = <2>;
     56
     57		partitions {
     58			compatible = "fixed-partitions";
     59			#address-cells = <1>;
     60			#size-cells = <1>;
     61
     62			kernel@0 {
     63				label = "kernel";
     64				reg = <0x0 0x200000>;
     65			};
     66
     67			rootfs@200000 {
     68				label = "rootfs";
     69				reg = <0x200000 0x600000>;
     70			};
     71		};
     72	};
     73};
     74
     75&macb0 {
     76	phy-mode = "mii";
     77	status = "okay";
     78};
     79
     80&pinctrl {
     81	board {
     82		pinctrl_pck0_as_mck: pck0_as_mck {
     83			atmel,pins = <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
     84		};
     85	};
     86
     87	spi0 {
     88		pinctrl_spi0: spi0-0 {
     89			atmel,pins =
     90				<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
     91				 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE
     92				 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
     93		};
     94
     95		pinctrl_spi0_npcs0: spi0_npcs0 {
     96			atmel,pins = <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
     97		};
     98
     99		pinctrl_spi0_npcs1: spi0_npcs1 {
    100			atmel,pins = <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
    101		};
    102	};
    103
    104	spi1 {
    105		pinctrl_spi1: spi1-0 {
    106			atmel,pins =
    107				<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE
    108				 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE
    109				 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
    110		};
    111
    112		pinctrl_spi1_npcs0: spi1_npcs0 {
    113			atmel,pins = <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
    114		};
    115
    116		pinctrl_spi1_npcs1: spi1_npcs1 {
    117			atmel,pins = <AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
    118		};
    119	};
    120};
    121
    122&spi0 {
    123	pinctrl-names = "default";
    124	pinctrl-0 = <&pinctrl_spi0 &pinctrl_spi0_npcs0 &pinctrl_spi0_npcs1>;
    125	cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>;
    126	status = "okay";
    127
    128	flash@0 {
    129		compatible = "jedec,spi-nor";
    130		spi-max-frequency = <20000000>;
    131		reg = <0>;
    132		#address-cells = <1>;
    133		#size-cells = <1>;
    134
    135		at91boot@0 {
    136			label = "at91boot";
    137			reg = <0x0 0x4000>;
    138		};
    139
    140		uenv@4000 {
    141			label = "uboot-env";
    142			reg = <0x4000 0x4000>;
    143		};
    144
    145		uboot@8000 {
    146			label = "uboot";
    147			reg = <0x8000 0x3E000>;
    148		};
    149	};
    150};
    151
    152&spi1 {
    153	pinctrl-names = "default";
    154	pinctrl-0 = <&pinctrl_spi1 &pinctrl_spi1_npcs0 &pinctrl_spi1_npcs1>;
    155	cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>, <&pioC 5 GPIO_ACTIVE_LOW>, <0>, <0>;
    156	status = "okay";
    157};
    158
    159&usart0 {
    160	pinctrl-0 =
    161		<&pinctrl_usart0
    162		 &pinctrl_usart0_rts
    163		 &pinctrl_usart0_cts
    164		 &pinctrl_usart0_dtr_dsr
    165		 &pinctrl_usart0_dcd
    166		 &pinctrl_usart0_ri>;
    167	status = "okay";
    168};
    169
    170&usb0 {
    171	num-ports = <2>;
    172	status = "okay";
    173};
    174
    175&usb1 {
    176	status = "okay";
    177};
    178
    179&watchdog {
    180	status = "okay";
    181};