cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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at91-sama5d27_som1.dtsi (3501B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board
      4 *
      5 *  Copyright (c) 2017, Microchip Technology Inc.
      6 *                2017 Cristian Birsan <cristian.birsan@microchip.com>
      7 *                2017 Claudiu Beznea <claudiu.beznea@microchip.com>
      8 */
      9#include "sama5d2.dtsi"
     10#include "sama5d2-pinfunc.h"
     11#include <dt-bindings/gpio/gpio.h>
     12
     13/ {
     14	model = "Atmel SAMA5D27 SoM1";
     15	compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
     16
     17	aliases {
     18		i2c0	= &i2c0;
     19	};
     20
     21	clocks {
     22		slow_xtal {
     23			clock-frequency = <32768>;
     24		};
     25
     26		main_xtal {
     27			clock-frequency = <24000000>;
     28		};
     29	};
     30
     31	ahb {
     32		sdmmc0: sdio-host@a0000000 {
     33			microchip,sdcal-inverted;
     34		};
     35
     36		apb {
     37			qspi1: spi@f0024000 {
     38				pinctrl-names = "default";
     39				pinctrl-0 = <&pinctrl_qspi1_default>;
     40
     41				flash@0 {
     42					#address-cells = <1>;
     43					#size-cells = <1>;
     44					compatible = "jedec,spi-nor";
     45					reg = <0>;
     46					spi-max-frequency = <80000000>;
     47					spi-tx-bus-width = <4>;
     48					spi-rx-bus-width = <4>;
     49					m25p,fast-read;
     50
     51					at91bootstrap@0 {
     52						label = "at91bootstrap";
     53						reg = <0x00000000 0x00040000>;
     54					};
     55
     56					bootloader@40000 {
     57						label = "bootloader";
     58						reg = <0x00040000 0x000c0000>;
     59					};
     60
     61					bootloaderenvred@100000 {
     62						label = "bootloader env redundant";
     63						reg = <0x00100000 0x00040000>;
     64					};
     65
     66					bootloaderenv@140000 {
     67						label = "bootloader env";
     68						reg = <0x00140000 0x00040000>;
     69					};
     70
     71					dtb@180000 {
     72						label = "device tree";
     73						reg = <0x00180000 0x00080000>;
     74					};
     75
     76					kernel@200000 {
     77						label = "kernel";
     78						reg = <0x00200000 0x00600000>;
     79					};
     80				};
     81			};
     82
     83			macb0: ethernet@f8008000 {
     84				pinctrl-names = "default";
     85				pinctrl-0 = <&pinctrl_macb0_default>;
     86				phy-mode = "rmii";
     87
     88				ethernet-phy@7 {
     89					reg = <0x7>;
     90					interrupt-parent = <&pioA>;
     91					interrupts = <PIN_PD31 IRQ_TYPE_LEVEL_LOW>;
     92					pinctrl-names = "default";
     93					pinctrl-0 = <&pinctrl_macb0_phy_irq>;
     94				};
     95			};
     96
     97			i2c0: i2c@f8028000 {
     98				dmas = <0>, <0>;
     99				pinctrl-names = "default", "gpio";
    100				pinctrl-0 = <&pinctrl_i2c0_default>;
    101				pinctrl-1 = <&pinctrl_i2c0_gpio>;
    102				sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
    103				scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
    104				status = "okay";
    105
    106				at24@50 {
    107					compatible = "atmel,24c02";
    108					reg = <0x50>;
    109					pagesize = <8>;
    110				};
    111			};
    112
    113			pinctrl@fc038000 {
    114				pinctrl_i2c0_default: i2c0_default {
    115					pinmux = <PIN_PD21__TWD0>,
    116						 <PIN_PD22__TWCK0>;
    117					bias-disable;
    118				};
    119
    120				pinctrl_i2c0_gpio: i2c0_gpio {
    121					pinmux = <PIN_PD21__GPIO>,
    122						 <PIN_PD22__GPIO>;
    123					bias-disable;
    124				};
    125
    126				pinctrl_qspi1_default: qspi1_default {
    127					sck_cs {
    128						pinmux = <PIN_PB5__QSPI1_SCK>,
    129							 <PIN_PB6__QSPI1_CS>;
    130						bias-disable;
    131					};
    132
    133					data {
    134						pinmux = <PIN_PB7__QSPI1_IO0>,
    135							 <PIN_PB8__QSPI1_IO1>,
    136							 <PIN_PB9__QSPI1_IO2>,
    137							 <PIN_PB10__QSPI1_IO3>;
    138						bias-pull-up;
    139					};
    140				};
    141
    142				pinctrl_macb0_default: macb0_default {
    143					pinmux = <PIN_PD9__GTXCK>,
    144						 <PIN_PD10__GTXEN>,
    145						 <PIN_PD11__GRXDV>,
    146						 <PIN_PD12__GRXER>,
    147						 <PIN_PD13__GRX0>,
    148						 <PIN_PD14__GRX1>,
    149						 <PIN_PD15__GTX0>,
    150						 <PIN_PD16__GTX1>,
    151						 <PIN_PD17__GMDC>,
    152						 <PIN_PD18__GMDIO>;
    153					bias-disable;
    154				};
    155
    156				pinctrl_macb0_phy_irq: macb0_phy_irq {
    157					pinmux = <PIN_PD31__GPIO>;
    158					bias-disable;
    159				};
    160			};
    161		};
    162	};
    163};