cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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at91-sama5d27_wlsom1.dtsi (8078B)


      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * at91-sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1
      4 *
      5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
      6 *
      7 * Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
      8 * Author: Eugen Hristev <eugen.hristev@microcihp.com>
      9 */
     10#include "sama5d2.dtsi"
     11#include "sama5d2-pinfunc.h"
     12#include <dt-bindings/gpio/gpio.h>
     13#include <dt-bindings/mfd/atmel-flexcom.h>
     14#include <dt-bindings/pinctrl/at91.h>
     15
     16/ {
     17	model = "Microchip SAMA5D27 WLSOM1";
     18	compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
     19
     20	aliases {
     21		i2c0 = &i2c0;
     22	};
     23
     24	clocks {
     25		slow_xtal {
     26			clock-frequency = <32768>;
     27		};
     28
     29		main_xtal {
     30			clock-frequency = <24000000>;
     31		};
     32	};
     33
     34	wifi_pwrseq: wifi_pwrseq {
     35		compatible = "mmc-pwrseq-wilc1000";
     36		reset-gpios = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
     37		powerdown-gpios = <&pioA PIN_PA29 GPIO_ACTIVE_HIGH>;
     38		pinctrl-0 = <&pinctrl_wilc_pwrseq>;
     39		pinctrl-names = "default";
     40	};
     41};
     42
     43&flx1 {
     44	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
     45
     46	uart6: serial@200 {
     47		pinctrl-0 = <&pinctrl_flx1_default>;
     48		pinctrl-names = "default";
     49	};
     50};
     51
     52&i2c0 {
     53	pinctrl-0 = <&pinctrl_i2c0_default>;
     54	pinctrl-1 = <&pinctrl_i2c0_gpio>;
     55	pinctrl-names = "default", "gpio";
     56	sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
     57	scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
     58	status = "okay";
     59};
     60
     61&i2c1 {
     62	dmas = <0>, <0>;
     63	pinctrl-names = "default", "gpio";
     64	pinctrl-0 = <&pinctrl_i2c1_default>;
     65	pinctrl-1 = <&pinctrl_i2c1_gpio>;
     66	sda-gpios = <&pioA PIN_PD19 GPIO_ACTIVE_HIGH>;
     67	scl-gpios = <&pioA PIN_PD20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
     68	status = "okay";
     69
     70	mcp16502@5b {
     71		compatible = "microchip,mcp16502";
     72		reg = <0x5b>;
     73		status = "okay";
     74		lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>;
     75
     76		regulators {
     77			vdd_3v3: VDD_IO {
     78				regulator-name = "VDD_IO";
     79				regulator-min-microvolt = <1200000>;
     80				regulator-max-microvolt = <3700000>;
     81				regulator-initial-mode = <2>;
     82				regulator-allowed-modes = <2>, <4>;
     83				regulator-always-on;
     84
     85				regulator-state-standby {
     86					regulator-on-in-suspend;
     87					regulator-mode = <4>;
     88				};
     89
     90				regulator-state-mem {
     91					regulator-off-in-suspend;
     92					regulator-mode = <4>;
     93				};
     94			};
     95
     96			vddio_ddr: VDD_DDR {
     97				regulator-name = "VDD_DDR";
     98				regulator-min-microvolt = <600000>;
     99				regulator-max-microvolt = <1850000>;
    100				regulator-initial-mode = <2>;
    101				regulator-allowed-modes = <2>, <4>;
    102				regulator-always-on;
    103
    104				regulator-state-standby {
    105					regulator-on-in-suspend;
    106					regulator-suspend-microvolt = <1200000>;
    107					regulator-changeable-in-suspend;
    108					regulator-mode = <4>;
    109				};
    110
    111				regulator-state-mem {
    112					regulator-on-in-suspend;
    113					regulator-suspend-microvolt = <1200000>;
    114					regulator-changeable-in-suspend;
    115					regulator-mode = <4>;
    116				};
    117			};
    118
    119			vdd_core: VDD_CORE {
    120				regulator-name = "VDD_CORE";
    121				regulator-min-microvolt = <600000>;
    122				regulator-max-microvolt = <1850000>;
    123				regulator-initial-mode = <2>;
    124				regulator-allowed-modes = <2>, <4>;
    125				regulator-always-on;
    126
    127				regulator-state-standby {
    128					regulator-on-in-suspend;
    129					regulator-mode = <4>;
    130				};
    131
    132				regulator-state-mem {
    133					regulator-off-in-suspend;
    134					regulator-mode = <4>;
    135				};
    136			};
    137
    138			vdd_ddr: VDD_OTHER {
    139				regulator-name = "VDD_OTHER";
    140				regulator-min-microvolt = <1800000>;
    141				regulator-max-microvolt = <1800000>;
    142				regulator-initial-mode = <2>;
    143				regulator-allowed-modes = <2>, <4>;
    144				regulator-always-on;
    145
    146				regulator-state-standby {
    147					regulator-on-in-suspend;
    148					regulator-suspend-microvolt = <1800000>;
    149					regulator-changeable-in-suspend;
    150					regulator-mode = <4>;
    151				};
    152
    153				regulator-state-mem {
    154					regulator-on-in-suspend;
    155					regulator-suspend-microvolt = <1800000>;
    156					regulator-changeable-in-suspend;
    157					regulator-mode = <4>;
    158				};
    159			};
    160
    161			LDO1 {
    162				regulator-name = "LDO1";
    163				regulator-min-microvolt = <1200000>;
    164				regulator-max-microvolt = <3700000>;
    165				regulator-always-on;
    166
    167				regulator-state-standby {
    168					regulator-on-in-suspend;
    169				};
    170
    171				regulator-state-mem {
    172					regulator-off-in-suspend;
    173				};
    174			};
    175
    176			LDO2 {
    177				regulator-name = "LDO2";
    178				regulator-min-microvolt = <1200000>;
    179				regulator-max-microvolt = <3700000>;
    180				regulator-always-on;
    181
    182				regulator-state-standby {
    183					regulator-on-in-suspend;
    184				};
    185
    186				regulator-state-mem {
    187					regulator-off-in-suspend;
    188				};
    189			};
    190		};
    191	};
    192};
    193
    194&macb0 {
    195	pinctrl-names = "default";
    196	pinctrl-0 = <&pinctrl_macb0_default>;
    197	phy-mode = "rmii";
    198
    199	ethernet-phy@0 {
    200		reg = <0x0>;
    201		interrupt-parent = <&pioA>;
    202		interrupts = <PIN_PB24 IRQ_TYPE_LEVEL_LOW>;
    203		pinctrl-names = "default";
    204		pinctrl-0 = <&pinctrl_macb0_phy_irq>;
    205	};
    206};
    207
    208&pmc {
    209	atmel,osc-bypass;
    210};
    211
    212&qspi1 {
    213	pinctrl-names = "default";
    214	pinctrl-0 = <&pinctrl_qspi1_default>;
    215	status = "disabled";
    216
    217	qspi1_flash: flash@0 {
    218		#address-cells = <1>;
    219		#size-cells = <1>;
    220		compatible = "jedec,spi-nor";
    221		reg = <0>;
    222		spi-max-frequency = <80000000>;
    223		spi-rx-bus-width = <4>;
    224		spi-tx-bus-width = <4>;
    225		m25p,fast-read;
    226		status = "disabled";
    227
    228		at91bootstrap@0 {
    229			label = "at91bootstrap";
    230			reg = <0x0 0x40000>;
    231		};
    232
    233		bootloader@40000 {
    234			label = "bootloader";
    235			reg = <0x40000 0xc0000>;
    236		};
    237
    238		bootloaderenvred@100000 {
    239			label = "bootloader env redundant";
    240			reg = <0x100000 0x40000>;
    241		};
    242
    243		bootloaderenv@140000 {
    244			label = "bootloader env";
    245			reg = <0x140000 0x40000>;
    246		};
    247
    248		dtb@180000 {
    249			label = "device tree";
    250			reg = <0x180000 0x80000>;
    251		};
    252
    253		kernel@200000 {
    254			label = "kernel";
    255			reg = <0x200000 0x600000>;
    256		};
    257	};
    258};
    259
    260&pioA {
    261	pinctrl_flx1_default: flx1_usart_default {
    262		pinmux = <PIN_PA24__FLEXCOM1_IO0>,
    263			 <PIN_PA23__FLEXCOM1_IO1>,
    264			 <PIN_PA25__FLEXCOM1_IO3>,
    265			 <PIN_PA26__FLEXCOM1_IO4>;
    266		bias-disable;
    267	};
    268
    269	pinctrl_i2c0_default: i2c0_default {
    270		pinmux = <PIN_PD21__TWD0>,
    271			 <PIN_PD22__TWCK0>;
    272		bias-disable;
    273	};
    274
    275	pinctrl_i2c0_gpio: i2c0_gpio {
    276		pinmux = <PIN_PD21__GPIO>,
    277			 <PIN_PD22__GPIO>;
    278		bias-disable;
    279	};
    280
    281	pinctrl_i2c1_default: i2c1_default {
    282		pinmux = <PIN_PD19__TWD1>,
    283			 <PIN_PD20__TWCK1>;
    284		bias-disable;
    285	};
    286
    287	pinctrl_i2c1_gpio: i2c1_gpio {
    288		pinmux = <PIN_PD19__GPIO>,
    289			 <PIN_PD20__GPIO>;
    290		bias-disable;
    291	};
    292
    293	pinctrl_macb0_default: macb0_default {
    294		pinmux = <PIN_PB14__GTXCK>,
    295			 <PIN_PB15__GTXEN>,
    296			 <PIN_PB16__GRXDV>,
    297			 <PIN_PB17__GRXER>,
    298			 <PIN_PB18__GRX0>,
    299			 <PIN_PB19__GRX1>,
    300			 <PIN_PB20__GTX0>,
    301			 <PIN_PB21__GTX1>,
    302			 <PIN_PB22__GMDC>,
    303			 <PIN_PB23__GMDIO>;
    304		bias-disable;
    305	};
    306
    307	pinctrl_macb0_phy_irq: macb0_phy_irq {
    308		pinmux = <PIN_PB24__GPIO>;
    309		bias-disable;
    310	};
    311
    312	pinctrl_qspi1_default: qspi1_default {
    313		pinmux = <PIN_PB5__QSPI1_SCK>,
    314			 <PIN_PB6__QSPI1_CS>,
    315			 <PIN_PB7__QSPI1_IO0>,
    316			 <PIN_PB8__QSPI1_IO1>,
    317			 <PIN_PB9__QSPI1_IO2>,
    318			 <PIN_PB10__QSPI1_IO3>;
    319		bias-pull-up;
    320	};
    321
    322	pinctrl_sdmmc1_default: sdmmc1_default {
    323		cmd-data {
    324			pinmux = <PIN_PA28__SDMMC1_CMD>,
    325				 <PIN_PA18__SDMMC1_DAT0>,
    326				 <PIN_PA19__SDMMC1_DAT1>,
    327				 <PIN_PA20__SDMMC1_DAT2>,
    328				 <PIN_PA21__SDMMC1_DAT3>;
    329			bias-disable;
    330		};
    331
    332		conf-ck {
    333			pinmux = <PIN_PA22__SDMMC1_CK>;
    334			bias-disable;
    335		};
    336	};
    337
    338	pinctrl_wilc_default: wilc_default {
    339		conf-irq {
    340			pinmux = <PIN_PB25__GPIO>;
    341			bias-disable;
    342		};
    343	};
    344
    345	pinctrl_wilc_pwrseq: wilc_pwrseq {
    346		conf-ce-nrst {
    347			pinmux = <PIN_PA27__GPIO>,
    348				 <PIN_PA29__GPIO>;
    349			bias-disable;
    350		};
    351
    352		conf-rtcclk {
    353			pinmux = <PIN_PB13__PCK1>;
    354			bias-disable;
    355		};
    356	};
    357};
    358
    359&sdmmc1 {
    360	#address-cells = <1>;
    361	#size-cells = <0>;
    362	bus-width = <4>;
    363	pinctrl-names = "default";
    364	pinctrl-0 = <&pinctrl_sdmmc1_default>;
    365	mmc-pwrseq = <&wifi_pwrseq>;
    366	no-1-8-v;
    367	non-removable;
    368	bus-width = <4>;
    369	status = "okay";
    370
    371	wilc: wifi@0 {
    372		reg = <0>;
    373		compatible = "microchip,wilc1000";
    374		pinctrl-names = "default";
    375		pinctrl-0 = <&pinctrl_wilc_default>;
    376		clocks = <&pmc PMC_TYPE_SYSTEM 9>;
    377		clock-names = "rtc";
    378		interrupts = <PIN_PB25 IRQ_TYPE_NONE>;
    379		interrupt-parent = <&pioA>;
    380		assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>;
    381		assigned-clock-rates = <32768>;
    382	};
    383};
    384