cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

at91-sama5d3_ksz9477_evb.dts (3941B)

      1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
      2/*
      3 * Copyright (c) 2021 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
      4 */
      5/dts-v1/;
      6#include "sama5d36.dtsi"
      7
      8/ {
      9	model = "EVB-KSZ9477";
     10	compatible = "microchip,sama5d3-ksz9477-evb", "atmel,sama5d36",
     11		     "atmel,sama5d3", "atmel,sama5";
     12
     13	chosen {
     14		stdout-path = &dbgu;
     15	};
     16
     17	reg_3v3: regulator-3v3 {
     18		compatible = "regulator-fixed";
     19		regulator-name = "3v3";
     20		regulator-min-microvolt = <3300000>;
     21		regulator-max-microvolt = <3300000>;
     22	};
     23
     24	reg_vcc_mmc0: regulator-mmc0 {
     25		compatible = "regulator-fixed";
     26		pinctrl-names = "default";
     27		pinctrl-0 = <&pinctrl_mcc0_vcc>;
     28		regulator-name = "mmc0-vcc";
     29		regulator-max-microvolt = <3300000>;
     30		regulator-min-microvolt = <3300000>;
     31		gpio = <&pioE 2 GPIO_ACTIVE_LOW>;
     32	};
     33};
     34
     35&dbgu {
     36	status = "okay";
     37};
     38
     39&ebi {
     40	pinctrl-0 = <&pinctrl_ebi_nand_addr>;
     41	pinctrl-names = "default";
     42	status = "okay";
     43};
     44
     45&i2c0 {
     46	pinctrl-0 = <&pinctrl_i2c0_pu>;
     47	status = "okay";
     48};
     49
     50&macb0 {
     51	phy-mode = "rgmii";
     52	status = "okay";
     53
     54	fixed-link {
     55		speed = <1000>;
     56		full-duplex;
     57	};
     58};
     59
     60&main_xtal {
     61	clock-frequency = <12000000>;
     62};
     63
     64&mmc0 {
     65	pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3
     66		     &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>;
     67	status = "okay";
     68
     69	slot@0 {
     70		reg = <0>;
     71		bus-width = <8>;
     72		cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>;
     73		disable-wp;
     74		vmmc-supply = <&reg_vcc_mmc0>;
     75		vqmmc-supply = <&reg_3v3>;
     76	};
     77};
     78
     79&nand_controller {
     80	status = "okay";
     81
     82	nand@3 {
     83		reg = <0x3 0x0 0x2>;
     84		atmel,rb = <0>;
     85		nand-bus-width = <8>;
     86		nand-ecc-mode = "hw";
     87		nand-ecc-strength = <4>;
     88		nand-ecc-step-size = <512>;
     89		nand-on-flash-bbt;
     90		label = "atmel_nand";
     91	};
     92};
     93
     94&slow_xtal {
     95	clock-frequency = <32768>;
     96};
     97
     98&spi0 {
     99	cs-gpios = <&pioD 13 GPIO_ACTIVE_LOW>, <0>, <0>,
    100		   <&pioD 16 GPIO_ACTIVE_LOW>;
    101	status = "okay";
    102};
    103
    104&spi1 {
    105	pinctrl-0 = <&pinctrl_spi_ksz>;
    106	cs-gpios = <&pioC 25 GPIO_ACTIVE_LOW>;
    107	status = "okay";
    108
    109	switch@0 {
    110		compatible = "microchip,ksz9477";
    111		reg = <0>;
    112		spi-max-frequency = <1000000>;
    113		spi-cpha;
    114		spi-cpol;
    115
    116		ports {
    117			#address-cells = <1>;
    118			#size-cells = <0>;
    119
    120			port@0 {
    121				reg = <0>;
    122				label = "lan1";
    123				phy-mode = "internal";
    124			};
    125
    126			port@1 {
    127				reg = <1>;
    128				label = "lan2";
    129				phy-mode = "internal";
    130			};
    131
    132			port@2 {
    133				reg = <2>;
    134				label = "lan3";
    135				phy-mode = "internal";
    136			};
    137
    138			port@3 {
    139				reg = <3>;
    140				label = "lan4";
    141				phy-mode = "internal";
    142			};
    143
    144			port@4 {
    145				reg = <4>;
    146				label = "lan5";
    147				phy-mode = "internal";
    148			};
    149
    150			port@5 {
    151				reg = <5>;
    152				label = "cpu";
    153				ethernet = <&macb0>;
    154				phy-mode = "rgmii-txid";
    155
    156				fixed-link {
    157					speed = <1000>;
    158					full-duplex;
    159				};
    160			};
    161		};
    162	};
    163};
    164
    165&usb0 {
    166	pinctrl-names = "default";
    167	pinctrl-0 = <&pinctrl_usba_vbus>;
    168	atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>;
    169	status = "okay";
    170};
    171
    172&pinctrl {
    173	board {
    174		pinctrl_i2c0_pu: i2c0-pu {
    175			atmel,pins =
    176				<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
    177				<AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
    178		};
    179
    180		pinctrl_mmc0_cd: mmc0-cd {
    181			atmel,pins = <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
    182		};
    183
    184		pinctrl_mcc0_vcc: mmc0-vcc {
    185			atmel,pins = <AT91_PIOE 2 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
    186		};
    187
    188		pinctrl_spi_ksz: spi-ksz {
    189			atmel,pins =
    190				<
    191				/* SPI1_MISO */
    192				AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
    193				/* SPI1_MOSI */
    194				AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE
    195				/* SPI1_SPCK */
    196				AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE
    197
    198				/* SPI CS */
    199				AT91_PIOC 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
    200				/* switch IRQ */
    201				AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH
    202				/* switch PME_N, SoC IN */
    203				AT91_PIOC 30 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP
    204				/* switch RST */
    205				AT91_PIOC 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH
    206				>;
    207		};
    208
    209		pinctrl_usba_vbus: usba-vbus {
    210			atmel,pins =
    211				<AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
    212		};
    213	};
    214};