cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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at91-wb50n.dts (1509B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * at91-wb50n.dts - Device Tree file for wb50n evaluation board
      4 *
      5 *  Copyright (C) 2018 Laird
      6 *
      7 */
      8
      9/dts-v1/;
     10#include "at91-wb50n.dtsi"
     11
     12/ {
     13	model = "Laird Workgroup Bridge 50N - Atmel SAMA5D";
     14	compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
     15
     16	gpio_keys {
     17		compatible = "gpio-keys";
     18		#address-cells = <1>;
     19		#size-cells = <0>;
     20
     21		btn0@10 {
     22			reg = <10>;
     23			label = "BTNESC";
     24			linux,code = <1>; /* ESC button */
     25			gpios = <&pioA 10 GPIO_ACTIVE_LOW>;
     26			wakeup-source;
     27		};
     28
     29		irqbtn@31 {
     30			reg = <31>;
     31			label = "IRQBTN";
     32			linux,code = <99>; /* SysReq button */
     33			gpios = <&pioE 31 GPIO_ACTIVE_LOW>;
     34			wakeup-source;
     35		};
     36	};
     37
     38	leds {
     39		compatible = "gpio-leds";
     40
     41		led0 {
     42			label = "wb50n:blue:led0";
     43			gpios = <&pioA 12 GPIO_ACTIVE_LOW>;
     44			default-state = "off";
     45		};
     46
     47		led1 {
     48			label = "wb50n:green:led1";
     49			gpios = <&pioA 24 GPIO_ACTIVE_LOW>;
     50			default-state = "off";
     51		};
     52
     53		led2 {
     54			label = "wb50n:red:led2";
     55			gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
     56			default-state = "off";
     57		};
     58	};
     59};
     60
     61&watchdog {
     62	status = "okay";
     63};
     64
     65&mmc0 {
     66	status = "okay";
     67};
     68
     69&macb1 {
     70	status = "okay";
     71};
     72
     73&dbgu {
     74	status = "okay";
     75};
     76
     77/* On BB40 this port is labeled UART1 */
     78&usart0 {
     79	status = "okay";
     80};
     81
     82/* On BB40 this port is labeled UART0 */
     83&usart1 {
     84	status = "okay";
     85};
     86
     87&i2c0 {
     88	status = "okay";
     89};
     90
     91&spi1 {
     92	status = "okay";
     93};
     94
     95&usb0 {
     96	status = "okay";
     97};
     98
     99&usb1 {
    100	status = "okay";
    101};
    102
    103&usb2 {
    104	status = "okay";
    105};
    106