cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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bcm-cygnus-clock.dtsi (3975B)

      1/*
      2 *  BSD LICENSE
      3 *
      4 *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
      5 *
      6 *  Redistribution and use in source and binary forms, with or without
      7 *  modification, are permitted provided that the following conditions
      8 *  are met:
      9 *
     10 *    * Redistributions of source code must retain the above copyright
     11 *      notice, this list of conditions and the following disclaimer.
     12 *    * Redistributions in binary form must reproduce the above copyright
     13 *      notice, this list of conditions and the following disclaimer in
     14 *      the documentation and/or other materials provided with the
     15 *      distribution.
     16 *    * Neither the name of Broadcom Corporation nor the names of its
     17 *      contributors may be used to endorse or promote products derived
     18 *      from this software without specific prior written permission.
     19 *
     20 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     21 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     22 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
     23 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
     24 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     25 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     26 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31 */
     32
     33clocks {
     34	#address-cells = <1>;
     35	#size-cells = <1>;
     36	ranges;
     37
     38	osc: oscillator {
     39		#clock-cells = <0>;
     40		compatible = "fixed-clock";
     41		clock-frequency = <25000000>;
     42	};
     43
     44	/* Cygnus ARM PLL */
     45	armpll: armpll@19000000 {
     46		#clock-cells = <0>;
     47		compatible = "brcm,cygnus-armpll";
     48		clocks = <&osc>;
     49		reg = <0x19000000 0x1000>;
     50	};
     51
     52	/* peripheral clock for system timer */
     53	periph_clk: arm_periph_clk {
     54		#clock-cells = <0>;
     55		compatible = "fixed-factor-clock";
     56		clocks = <&armpll>;
     57		clock-div = <2>;
     58		clock-mult = <1>;
     59	};
     60
     61	/* APB bus clock */
     62	apb_clk: apb_clk {
     63		#clock-cells = <0>;
     64		compatible = "fixed-factor-clock";
     65		clocks = <&armpll>;
     66		clock-div = <4>;
     67		clock-mult = <1>;
     68	};
     69
     70	genpll: genpll@301d000 {
     71		#clock-cells = <1>;
     72		compatible = "brcm,cygnus-genpll";
     73		reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
     74		clocks = <&osc>;
     75		clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
     76				     "enet_sw", "audio_125", "can";
     77	};
     78
     79	/* always 1/2 of the axi21 clock */
     80	axi41_clk: axi41_clk {
     81		#clock-cells = <0>;
     82		compatible = "fixed-factor-clock";
     83		clocks = <&genpll 1>;
     84		clock-div = <2>;
     85		clock-mult = <1>;
     86	};
     87
     88	/* always 1/4 of the axi21 clock */
     89	axi81_clk: axi81_clk {
     90		#clock-cells = <0>;
     91		compatible = "fixed-factor-clock";
     92		clocks = <&genpll 1>;
     93		clock-div = <4>;
     94		clock-mult = <1>;
     95	};
     96
     97	lcpll0: lcpll0@301d02c {
     98		#clock-cells = <1>;
     99		compatible = "brcm,cygnus-lcpll0";
    100		reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>;
    101		clocks = <&osc>;
    102		clock-output-names = "lcpll0", "pcie_phy", "ddr_phy", "sdio",
    103				     "usb_phy", "smart_card", "ch5";
    104	};
    105
    106	mipipll: mipipll@180a9800 {
    107		#clock-cells = <1>;
    108		compatible = "brcm,cygnus-mipipll";
    109		reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>;
    110		clocks = <&osc>;
    111		clock-output-names = "mipipll", "ch0_unused", "ch1_lcd",
    112				     "ch2_v3d", "ch3_unused", "ch4_unused",
    113				     "ch5_unused";
    114	};
    115
    116	asiu_clks: asiu_clks@301d048 {
    117		#clock-cells = <1>;
    118		compatible = "brcm,cygnus-asiu-clk";
    119		reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
    120
    121		clocks = <&osc>;
    122		clock-output-names = "keypad", "adc/touch", "pwm";
    123	};
    124
    125	audiopll: audiopll@180aeb00 {
    126		#clock-cells = <1>;
    127		compatible = "brcm,cygnus-audiopll";
    128		reg = <0x180aeb00 0x68>;
    129		clocks = <&osc>;
    130		clock-output-names = "audiopll", "ch0_audio",
    131					"ch1_audio", "ch2_audio";
    132	};
    133};