cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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bcm2837-rpi-3-a-plus.dts (2974B)

      1// SPDX-License-Identifier: GPL-2.0
      2/dts-v1/;
      3#include "bcm2837.dtsi"
      4#include "bcm2836-rpi.dtsi"
      5#include "bcm283x-rpi-usb-host.dtsi"
      6#include "bcm283x-rpi-wifi-bt.dtsi"
      7
      8/ {
      9	compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837";
     10	model = "Raspberry Pi 3 Model A+";
     11
     12	chosen {
     13		/* 8250 auxiliary UART instead of pl011 */
     14		stdout-path = "serial1:115200n8";
     15	};
     16
     17	memory@0 {
     18		device_type = "memory";
     19		reg = <0 0x20000000>;
     20	};
     21
     22	leds {
     23		led-act {
     24			gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
     25		};
     26
     27		led-pwr {
     28			label = "PWR";
     29			gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
     30			default-state = "keep";
     31			linux,default-trigger = "default-on";
     32		};
     33	};
     34};
     35
     36&firmware {
     37	expgpio: gpio {
     38		compatible = "raspberrypi,firmware-gpio";
     39		gpio-controller;
     40		#gpio-cells = <2>;
     41		gpio-line-names = "",
     42				  "BT_WL_ON",
     43				  "STATUS_LED_R",
     44				  "",
     45				  "",
     46				  "CAM_GPIO0",
     47				  "CAM_GPIO1",
     48				  "";
     49		status = "okay";
     50	};
     51};
     52
     53&gpio {
     54	/*
     55	 * This is mostly based on the official GPU firmware DT blob.
     56	 *
     57	 * Legend:
     58	 * "FOO" = GPIO line named "FOO" on the schematic
     59	 * "FOO_N" = GPIO line named "FOO" on schematic, active low
     60	 */
     61	gpio-line-names = "ID_SDA",
     62			  "ID_SCL",
     63			  "SDA1",
     64			  "SCL1",
     65			  "GPIO_GCLK",
     66			  "GPIO5",
     67			  "GPIO6",
     68			  "SPI_CE1_N",
     69			  "SPI_CE0_N",
     70			  "SPI_MISO",
     71			  "SPI_MOSI",
     72			  "SPI_SCLK",
     73			  "GPIO12",
     74			  "GPIO13",
     75			  /* Serial port */
     76			  "TXD1",
     77			  "RXD1",
     78			  "GPIO16",
     79			  "GPIO17",
     80			  "GPIO18",
     81			  "GPIO19",
     82			  "GPIO20",
     83			  "GPIO21",
     84			  "GPIO22",
     85			  "GPIO23",
     86			  "GPIO24",
     87			  "GPIO25",
     88			  "GPIO26",
     89			  "GPIO27",
     90			  "HDMI_HPD_N",
     91			  "STATUS_LED_G",
     92			  /* Used by BT module */
     93			  "CTS0",
     94			  "RTS0",
     95			  "TXD0",
     96			  "RXD0",
     97			  /* Used by Wifi */
     98			  "SD1_CLK",
     99			  "SD1_CMD",
    100			  "SD1_DATA0",
    101			  "SD1_DATA1",
    102			  "SD1_DATA2",
    103			  "SD1_DATA3",
    104			  "PWM0_OUT",
    105			  "PWM1_OUT",
    106			  "", /* GPIO42 */
    107			  "WIFI_CLK",
    108			  "SDA0",
    109			  "SCL0",
    110			  "SMPS_SCL",
    111			  "SMPS_SDA",
    112			  /* Used by SD Card */
    113			  "SD_CLK_R",
    114			  "SD_CMD_R",
    115			  "SD_DATA0_R",
    116			  "SD_DATA1_R",
    117			  "SD_DATA2_R",
    118			  "SD_DATA3_R";
    119};
    120
    121&hdmi {
    122	hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
    123	power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
    124	status = "okay";
    125};
    126
    127&pwm {
    128	pinctrl-names = "default";
    129	pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
    130	status = "okay";
    131};
    132
    133/* SDHOST is used to drive the SD card */
    134&sdhost {
    135	pinctrl-names = "default";
    136	pinctrl-0 = <&sdhost_gpio48>;
    137	status = "okay";
    138	bus-width = <4>;
    139};
    140
    141/* uart0 communicates with the BT module
    142 *
    143 * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven
    144 * by a single GPIO. We can't give GPIO control to one of the drivers,
    145 * otherwise the other part would get unexpectedly disturbed.
    146 */
    147&uart0 {
    148	pinctrl-names = "default";
    149	pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
    150};
    151
    152/* uart1 is mapped to the pin header */
    153&uart1 {
    154	pinctrl-names = "default";
    155	pinctrl-0 = <&uart1_gpio14>;
    156	status = "okay";
    157};