cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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bcm47189-luxul-xap-810.dts (1489B)

      1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
      2/*
      3 * Copyright 2017 Luxul Inc.
      4 */
      5
      6/dts-v1/;
      7
      8#include "bcm53573.dtsi"
      9
     10/ {
     11	compatible = "luxul,xap-810-v1", "brcm,bcm47189", "brcm,bcm53573";
     12	model = "Luxul XAP-810 V1";
     13
     14	chosen {
     15		bootargs = "earlycon";
     16	};
     17
     18	memory@0 {
     19		device_type = "memory";
     20		reg = <0x00000000 0x08000000>;
     21	};
     22
     23	leds {
     24		compatible = "gpio-leds";
     25
     26		5ghz {
     27			label = "bcm53xx:blue:5ghz";
     28			gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
     29			linux,default-trigger = "default-off";
     30		};
     31
     32		system {
     33			label = "bcm53xx:green:system";
     34			gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
     35			linux,default-trigger = "timer";
     36		};
     37	};
     38
     39	pcie0_leds {
     40		compatible = "gpio-leds";
     41
     42		2ghz {
     43			label = "bcm53xx:blue:2ghz";
     44			gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>;
     45			linux,default-trigger = "default-off";
     46		};
     47	};
     48
     49	gpio-keys {
     50		compatible = "gpio-keys";
     51
     52		restart {
     53			label = "Reset";
     54			linux,code = <KEY_RESTART>;
     55			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
     56		};
     57	};
     58};
     59
     60&pcie0 {
     61	ranges = <0x00000000 0 0 0 0 0x00100000>;
     62	#address-cells = <3>;
     63	#size-cells = <2>;
     64
     65	bridge@0,0,0 {
     66		reg = <0x0000 0 0 0 0>;
     67		ranges = <0x00000000 0 0 0 0 0 0 0x00100000>;
     68		#address-cells = <3>;
     69		#size-cells = <2>;
     70
     71		wifi@0,1,0 {
     72			reg = <0x0000 0 0 0 0>;
     73			ranges = <0x00000000 0 0 0 0x00100000>;
     74			#address-cells = <1>;
     75			#size-cells = <1>;
     76
     77			pcie0_chipcommon: chipcommon@0 {
     78				reg = <0 0x1000>;
     79
     80				gpio-controller;
     81				#gpio-cells = <2>;
     82			};
     83		};
     84	};
     85};