cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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bcm47622.dtsi (2779B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Copyright 2022 Broadcom Ltd.
      4 */
      5
      6#include <dt-bindings/interrupt-controller/arm-gic.h>
      7#include <dt-bindings/interrupt-controller/irq.h>
      8
      9/ {
     10	compatible = "brcm,bcm47622", "brcm,bcmbca";
     11	#address-cells = <1>;
     12	#size-cells = <1>;
     13
     14	interrupt-parent = <&gic>;
     15
     16	cpus {
     17		#address-cells = <1>;
     18		#size-cells = <0>;
     19
     20		CA7_0: cpu@0 {
     21			device_type = "cpu";
     22			compatible = "arm,cortex-a7";
     23			reg = <0x0>;
     24			next-level-cache = <&L2_0>;
     25			enable-method = "psci";
     26		};
     27
     28		CA7_1: cpu@1 {
     29			device_type = "cpu";
     30			compatible = "arm,cortex-a7";
     31			reg = <0x1>;
     32			next-level-cache = <&L2_0>;
     33			enable-method = "psci";
     34		};
     35		CA7_2: cpu@2 {
     36			device_type = "cpu";
     37			compatible = "arm,cortex-a7";
     38			reg = <0x2>;
     39			next-level-cache = <&L2_0>;
     40			enable-method = "psci";
     41		};
     42		CA7_3: cpu@3 {
     43			device_type = "cpu";
     44			compatible = "arm,cortex-a7";
     45			reg = <0x3>;
     46			next-level-cache = <&L2_0>;
     47			enable-method = "psci";
     48		};
     49		L2_0: l2-cache0 {
     50			compatible = "cache";
     51		};
     52	};
     53
     54	timer {
     55		compatible = "arm,armv7-timer";
     56		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
     57			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
     58			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
     59			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
     60		arm,cpu-registers-not-fw-configured;
     61	};
     62
     63	pmu: pmu {
     64		compatible = "arm,cortex-a7-pmu";
     65		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
     66			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
     67			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
     68			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
     69		interrupt-affinity = <&CA7_0>, <&CA7_1>,
     70			<&CA7_2>, <&CA7_3>;
     71	};
     72
     73	clocks: clocks {
     74		periph_clk: periph-clk {
     75			compatible = "fixed-clock";
     76			#clock-cells = <0>;
     77			clock-frequency = <200000000>;
     78		};
     79		uart_clk: uart-clk {
     80			compatible = "fixed-factor-clock";
     81			#clock-cells = <0>;
     82			clocks = <&periph_clk>;
     83			clock-div = <4>;
     84			clock-mult = <1>;
     85		};
     86	};
     87
     88	psci {
     89		compatible = "arm,psci-0.2";
     90		method = "smc";
     91		cpu_off = <1>;
     92		cpu_on = <2>;
     93	};
     94
     95	axi@81000000 {
     96		compatible = "simple-bus";
     97		#address-cells = <1>;
     98		#size-cells = <1>;
     99		ranges = <0 0x81000000 0x818000>;
    100
    101		gic: interrupt-controller@1000 {
    102			compatible = "arm,cortex-a7-gic";
    103			#interrupt-cells = <3>;
    104			#address-cells = <0>;
    105			interrupt-controller;
    106			reg = <0x1000 0x1000>,
    107				<0x2000 0x2000>;
    108		};
    109	};
    110
    111	bus@ff800000 {
    112		compatible = "simple-bus";
    113		#address-cells = <1>;
    114		#size-cells = <1>;
    115		ranges = <0 0xff800000 0x800000>;
    116
    117		uart0: serial@12000 {
    118			compatible = "arm,pl011", "arm,primecell";
    119			reg = <0x12000 0x1000>;
    120			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
    121			clocks = <&uart_clk>, <&uart_clk>;
    122			clock-names = "uartclk", "apb_pclk";
    123			status = "disabled";
    124		};
    125	};
    126};