cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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bcm947189acdbmr.dts (1733B)

      1/*
      2 * Copyright (C) 2017 Broadcom
      3 * Author: Florian Fainelli <f.fainelli@gmail.com>
      4 *
      5 * Licensed under the ISC license.
      6 */
      7
      8/dts-v1/;
      9
     10#include "bcm53573.dtsi"
     11
     12/ {
     13	compatible = "brcm,bcm947189acdbmr", "brcm,bcm47189", "brcm,bcm53573";
     14	model = "Broadcom BCM947189ACDBMR";
     15
     16	chosen {
     17		bootargs = "console=ttyS0,115200 earlycon";
     18	};
     19
     20	memory@0 {
     21		device_type = "memory";
     22		reg = <0x00000000 0x08000000>;
     23	};
     24
     25	leds {
     26		compatible = "gpio-leds";
     27
     28		wps {
     29			label = "bcm53xx:blue:wps";
     30			gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
     31		};
     32
     33		5ghz {
     34			label = "bcm53xx:blue:5ghz";
     35			gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
     36		};
     37
     38		2ghz {
     39			label = "bcm53xx:blue:2ghz";
     40			gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
     41		};
     42	};
     43
     44	gpio-keys {
     45		compatible = "gpio-keys";
     46
     47		restart {
     48			label = "Reset";
     49			linux,code = <KEY_RESTART>;
     50			gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
     51		};
     52
     53		wps {
     54			label = "WPS";
     55			linux,code = <KEY_WPS_BUTTON>;
     56			gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
     57		};
     58	};
     59
     60	spi {
     61		compatible = "spi-gpio";
     62		num-chipselects = <1>;
     63		gpio-sck = <&chipcommon 21 0>;
     64		gpio-miso = <&chipcommon 22 0>;
     65		gpio-mosi = <&chipcommon 23 0>;
     66		cs-gpios = <&chipcommon 24 0>;
     67		#address-cells = <1>;
     68		#size-cells = <0>;
     69
     70		/* External BCM6802 MoCA chip is connected */
     71	};
     72};
     73
     74&pcie0 {
     75	ranges = <0x00000000 0 0 0 0 0x00100000>;
     76	#address-cells = <3>;
     77	#size-cells = <2>;
     78
     79	bridge@0,0,0 {
     80		reg = <0x0000 0 0 0 0>;
     81		ranges = <0x00000000 0 0 0 0 0 0 0x00100000>;
     82		#address-cells = <3>;
     83		#size-cells = <2>;
     84
     85		wifi@0,1,0 {
     86			reg = <0x0000 0 0 0 0>;
     87			ranges = <0x00000000 0 0 0 0x00100000>;
     88			#address-cells = <1>;
     89			#size-cells = <1>;
     90		};
     91	};
     92};
     93
     94&usb2 {
     95	vcc-gpio = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
     96};