cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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berlin2cd-valve-steamlink.dts (1746B)

      1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
      2/*
      3 * Copyright 2018 Alexander Monakov <amonakov@gmail.com>
      4 */
      5/dts-v1/;
      6
      7#include "berlin2cd.dtsi"
      8#include <dt-bindings/gpio/gpio.h>
      9
     10/ {
     11	model = "Valve Steam Link";
     12	compatible = "valve,steamlink", "marvell,berlin2cd", "marvell,berlin";
     13
     14	memory@0 {
     15		device_type = "memory";
     16		reg = <0x00000000 0x20000000>; /* 512 MB */
     17	};
     18
     19	gpio-restart {
     20		compatible = "gpio-restart";
     21		gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
     22		active-delay = <100>;
     23		inactive-delay = <10>;
     24		wait-delay = <100>;
     25		priority = <200>;
     26	};
     27};
     28
     29&cpu {
     30	cpu-supply = <&vcpu>;
     31	operating-points = <
     32		/* kHz    uV */
     33		1000000 1325000
     34	>;
     35};
     36
     37&i2c0 {
     38	status = "okay";
     39
     40	/* There are two regulators on the board. One is accessible via I2C,
     41	 * with buck1 providing SoC power (set up by bootloader to 1.325V or
     42	 * less depending on leakage value in OTP), and buck2 likely used for
     43	 * DRAM (providing 1.35V). The other regulator on the opposite side
     44	 * of the board is probably supplying SDIO and NAND fixed voltages. */
     45	regulator@19 {
     46		compatible = "marvell,88pg868";
     47		reg = <0x19>;
     48
     49		vcpu: buck1 {
     50			regulator-boot-on;
     51			regulator-always-on;
     52			regulator-min-microvolt = <1000000>;
     53			regulator-max-microvolt = <1325000>;
     54		};
     55	};
     56};
     57
     58/* Fixed interface to on-board Marvell 8897 Wi-Fi/Bluetooth/NFC chip. */
     59&sdhci0 {
     60	keep-power-in-suspend;
     61	non-removable;
     62	status = "okay";
     63};
     64
     65&uart0 {
     66	/* RX/TX are routed to TP50/TP51 on the board. */
     67	status = "okay";
     68};
     69
     70/* The SoC is connected to on-board USB hub that in turn has one downstream
     71 * port wired to the on-board Steam Controller wireless receiver chip. */
     72&usb_phy1 { status = "okay"; };
     73
     74&usb1 {
     75	dr_mode = "host";
     76	status = "okay";
     77};
     78
     79&eth1 { status = "okay"; };