cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

cx92755.dtsi (4018B)

      1/*
      2 * Device Tree Include file for the Conexant Digicolor CX92755 SoC
      3 *
      4 * Author: Baruch Siach <baruch@tkos.co.il>
      5 *
      6 *  Copyright (C) 2014 Paradox Innovation Ltd.
      7 *
      8 * This file is dual-licensed: you can use it either under the terms
      9 * of the GPL or the X11 license, at your option. Note that this dual
     10 * licensing only applies to this file, and not this project as a
     11 * whole.
     12 *
     13 *  a) This file is free software; you can redistribute it and/or
     14 *     modify it under the terms of the GNU General Public License as
     15 *     published by the Free Software Foundation; either version 2 of the
     16 *     License, or (at your option) any later version.
     17 *
     18 *     This file is distributed in the hope that it will be useful,
     19 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
     20 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     21 *     GNU General Public License for more details.
     22 *
     23 * Or, alternatively,
     24 *
     25 *  b) Permission is hereby granted, free of charge, to any person
     26 *     obtaining a copy of this software and associated documentation
     27 *     files (the "Software"), to deal in the Software without
     28 *     restriction, including without limitation the rights to use,
     29 *     copy, modify, merge, publish, distribute, sublicense, and/or
     30 *     sell copies of the Software, and to permit persons to whom the
     31 *     Software is furnished to do so, subject to the following
     32 *     conditions:
     33 *
     34 *     The above copyright notice and this permission notice shall be
     35 *     included in all copies or substantial portions of the Software.
     36 *
     37 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     38 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
     39 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     40 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
     41 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
     42 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     43 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     44 *     OTHER DEALINGS IN THE SOFTWARE.
     45 */
     46
     47/ {
     48	#address-cells = <1>;
     49	#size-cells = <1>;
     50	compatible = "cnxt,cx92755";
     51
     52	interrupt-parent = <&intc>;
     53
     54	cpus {
     55		#address-cells = <1>;
     56		#size-cells = <0>;
     57		cpu@0 {
     58			device_type = "cpu";
     59			compatible = "arm,cortex-a8";
     60			reg = <0x0>;
     61		};
     62	};
     63
     64	main_clk: main_clk {
     65		compatible = "fixed-clock";
     66		#clock-cells = <0>;
     67		clock-frequency  = <200000000>;
     68	};
     69
     70	intc: interrupt-controller@f0000040 {
     71		compatible = "cnxt,cx92755-ic";
     72		interrupt-controller;
     73		#interrupt-cells = <1>;
     74		reg = <0xf0000040 0x40>;
     75		syscon = <&uc_regs>;
     76	};
     77
     78	timer@f0000fc0 {
     79		compatible = "cnxt,cx92755-timer";
     80		reg = <0xf0000fc0 0x40>;
     81		interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>;
     82		clocks = <&main_clk>;
     83	};
     84
     85	rtc@f0000c30 {
     86		compatible = "cnxt,cx92755-rtc";
     87		reg = <0xf0000c30 0x18>;
     88		interrupts = <25>;
     89	};
     90
     91	watchdog@f0000fc0 {
     92		compatible = "cnxt,cx92755-wdt";
     93		reg = <0xf0000fc0 0x8>;
     94		clocks = <&main_clk>;
     95		timeout-sec = <15>;
     96	};
     97
     98	pinctrl: pinctrl@f0000e20 {
     99		compatible = "cnxt,cx92755-pinctrl";
    100		reg = <0xf0000e20 0x100>;
    101		gpio-controller;
    102		#gpio-cells = <2>;
    103	};
    104
    105	uc_regs: syscon@f00003a0 {
    106		compatible = "cnxt,cx92755-uc", "syscon";
    107		reg = <0xf00003a0 0x10>;
    108	};
    109
    110	uart0: uart@f0000740 {
    111		compatible = "cnxt,cx92755-usart";
    112		reg = <0xf0000740 0x20>;
    113		clocks = <&main_clk>;
    114		interrupts = <44>;
    115		status = "disabled";
    116	};
    117
    118	uart1: uart@f0000760 {
    119		compatible = "cnxt,cx92755-usart";
    120		reg = <0xf0000760 0x20>;
    121		clocks = <&main_clk>;
    122		interrupts = <45>;
    123		status = "disabled";
    124	};
    125
    126	uart2: uart@f0000780 {
    127		compatible = "cnxt,cx92755-usart";
    128		reg = <0xf0000780 0x20>;
    129		clocks = <&main_clk>;
    130		interrupts = <46>;
    131		status = "disabled";
    132	};
    133
    134	i2c: i2c@f0000120 {
    135		compatible = "cnxt,cx92755-i2c";
    136		reg = <0xf0000120 0x10>;
    137		interrupts = <28>;
    138		clocks = <&main_clk>;
    139		clock-frequency = <100000>;
    140		#address-cells = <1>;
    141		#size-cells = <0>;
    142		status = "disabled";
    143	};
    144};